Nguyen Anh Quynh
8cdafda551
arm: add new field mem_barrier to cs_arm struct. this requires changes in bindings
2014-11-11 22:30:30 +08:00
Nguyen Anh Quynh
278e7270d9
arm: print immediate in positive form for AND/ORR/EOR/BIC instructions
2014-11-11 12:50:43 +08:00
Nguyen Anh Quynh
2ac5d79353
arm: print floating point number in %e format
2014-11-10 21:46:34 +08:00
Nguyen Anh Quynh
6acaaa5e44
arm: printAddrMode5Operand() is wrong on calculating subtracted variable
2014-11-10 17:41:05 +08:00
Nguyen Anh Quynh
4e17eefc57
arm: lowercase for apsr_nzcv
2014-11-10 17:02:32 +08:00
Nguyen Anh Quynh
d865f39a68
arm: use lowercase for special registers
2014-11-10 16:38:17 +08:00
Nguyen Anh Quynh
2593e22932
arm: support V8 as a mode for A32 encodings
2014-11-10 16:35:38 +08:00
Nguyen Anh Quynh
c2ea812ea7
fix cs_group_name() after the change on generic group ids
2014-10-31 15:36:19 +08:00
Nguyen Anh Quynh
c58e704517
do not need to explicitly assign values for operand types in the last commit
2014-10-31 13:55:18 +08:00
Nguyen Anh Quynh
21ac056728
use common operand types across all architectures. this adds cs_op_type to capstone.h. suggestion by @zneak
2014-10-31 13:08:28 +08:00
flyingsymbols
d91f964d40
* Fixed bug in Thumb2 pop caused by me incorrectly assuming that
...
ARM_SP == 13, ARM_LR == 14, and ARM_PC == 15, which is not the case
* updated CMakeLists to include building arm regression test
* added explicit casts for 64 bit visual studio 2012 build to get around
truncation warnings from size_t conversion
2014-10-23 12:04:23 -04:00
Nguyen Anh Quynh
11f8e7c596
arm: B, BL, BX, BLX, BXJ belong to ARM_GRP_JUMP group. issue reported by @nanomad
2014-10-21 17:35:34 +08:00
Nguyen Anh Quynh
8bf5fa60ad
arm: remove dead code
2014-10-07 07:56:01 +08:00
Nguyen Anh Quynh
b0cc71da59
bindings: update java/ocaml/python after the last change in Arm's core
2014-10-06 21:01:32 +08:00
Nguyen Anh Quynh
8fb2eab459
arm: some operands can get subtracted from base register, thus have '-' sign associated. this adds subtracted field into cs_arm_op to provide this info. issue reported by Yegor Derevenets
2014-10-06 20:27:25 +08:00
Nguyen Anh Quynh
9235fdc504
arm: The Thumb2 ldrexd and strexd instructions are not defined for M-class architectures
2014-09-30 07:44:50 +08:00
Nguyen Anh Quynh
d7e42b7d36
rename all the constants marking ending from _MAX to _ENDING. this also updates Java/Python/Ocaml bindings accordingly
2014-09-29 17:15:25 +08:00
Nguyen Anh Quynh
d442fbc06e
arm: t2BXJ also belongs to groups ARM_GRP_NOTMCLASS & ARM_GRP_PREV8
2014-09-26 10:38:29 +08:00
Nguyen Anh Quynh
4e87675c54
arm: relative branch should not be negative. bug reported by @acez
2014-09-23 16:49:12 +08:00
Yegor Derevenets
ced9d24e35
Workaround missing <inttypes.h> on MSVC 2010
2014-09-21 17:27:11 +02:00
Nguyen Anh Quynh
04d9f8ee17
arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes
2014-09-01 23:27:24 +08:00
Nguyen Anh Quynh
07c92ec20a
fix warnings reported by MSVC
2014-08-26 15:35:11 +08:00
Nguyen Anh Quynh
14b684e07d
last commit missed a check
2014-08-25 23:45:52 +08:00
Nguyen Anh Quynh
b1e87e3e31
arm, mips, ppc, spac, x86: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands
2014-08-25 23:27:33 +08:00
Nguyen Anh Quynh
7c089fd6c6
arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python & Java bindings accordingly
2014-08-13 23:08:40 +08:00
Nguyen Anh Quynh
b52f11f636
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
2014-08-13 22:38:15 +08:00
Nguyen Anh Quynh
590f23af54
arm: do not need to initialize local variable opcode in DecodeRegListOperand()
2014-07-31 21:23:51 +08:00
Nguyen Anh Quynh
0c235e15ab
arm: some simple improvements & cleanups
2014-07-31 21:16:54 +08:00
Nguyen Anh Quynh
26dfbc6677
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
2014-07-31 18:24:51 +08:00
Nguyen Anh Quynh
5d8067822b
Merge branch 'next' of https://github.com/flyingsymbols/capstone into arm
2014-07-31 15:36:13 +08:00
flyingsymbols
298d413bbc
* added a test file to suite for testing invalid and valid instruction sequences
...
* fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included)
* fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned)
* eliminated some warnings by explicitly casting so I could turn on
treat warnings as errors locally
General notes:
* probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes
( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have )
* the invalid pop was being treated as a soft fail which then gets coerced
to a success because it is != MCDisassembler_Fail in Thumb_getInstruction
what are the semantics of a soft fail? Maybe we should be able to set up
whether or not we want a soft fail to be a real fail in the csh struct?
2014-07-15 04:33:40 -04:00
Nguyen Anh Quynh
650f96ce43
add new API cs_group_name() to return group name in string, given the group id
2014-07-08 08:59:27 +08:00
Nguyen Anh Quynh
73eb5d5486
arm: op_addImm() is called only when detail mode is ON
2014-06-17 18:08:29 +08:00
Nguyen Anh Quynh
ebe2443b9b
arm: some special instructions need to have numerical operand added manually in printInstruction()
2014-06-17 13:56:01 +08:00
Nguyen Anh Quynh
73bbbb3800
arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bindings at the same time
2014-06-17 13:29:54 +08:00
Nguyen Anh Quynh
8693fcdc99
arm: correct operand setup for REG type in printAddrMode3OffsetOperand()
2014-06-17 13:28:33 +08:00
Nguyen Anh Quynh
2a461ed422
arm: zeroout a whole cs_arm struct in *getInstruction(). this makes sure operand of REG type has shift type = 0 by default
2014-06-17 13:27:38 +08:00
Nguyen Anh Quynh
495295ecd4
MCInst_Init() is arch-independent
2014-06-16 15:54:32 +08:00
Nguyen Anh Quynh
9678705d57
arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free
2014-06-10 13:59:55 +07:00
Nguyen Anh Quynh
748687df46
arm: convert the left-over MCOperand_CreateImm to MCOperand_CreateImm0
2014-06-10 09:18:39 +07:00
Nguyen Anh Quynh
0f648ea3e8
arm: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free to improve performance
2014-06-10 01:01:23 +07:00
Nguyen Anh Quynh
8c1104b567
arm: do not use markup
2014-06-10 00:39:06 +07:00
Nguyen Anh Quynh
dd9225b930
arm: use SStream_concat0() for SStream_concat() whereever possible for better performance
2014-06-10 00:37:53 +07:00
Nguyen Anh Quynh
69582d71ae
initialize cs_insn.detail by properly zero-out right members for each arch
2014-06-09 17:50:01 +07:00
Nguyen Anh Quynh
29fd0f6405
fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
2014-06-09 08:00:18 +07:00
Nguyen Anh Quynh
30c065998b
optimize memset() of MCInst_Init()
2014-06-07 13:30:59 +08:00
Nguyen Anh Quynh
c70442edc6
arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione
2014-06-01 11:35:34 +07:00
Nguyen Anh Quynh
a04ee4feb8
arm: add missing the check for detail mode in the last commit
2014-06-01 10:52:01 +07:00
Nguyen Anh Quynh
b79d915a38
arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione
2014-06-01 10:48:55 +07:00
Nguyen Anh Quynh
bb71c13098
arm: add missing operand info for Thumb instruction LDR involving label. bug reported by Daniel Colascione
2014-06-01 10:14:31 +07:00
