1745 Commits

Author SHA1 Message Date
Rot127
c14c245986 Set sysop members by their C++ type name.
Prevents build warnings of implicit enum convertions.
2023-07-22 09:08:11 -05:00
Rot127
fbb061620f Run clang-format (#2093) 2023-07-19 19:46:00 +08:00
Rot127
104f693c11 Architecture updater (auto-sync) - Updating ARM (#1949)
* Add auto-sync updater.

* Update Capstone core with auto-sync changes.

* Update ARM via auto-sync.

* Make changes to arch modules which are introduced by auto-sync.

* Update tests for ARM.

* Fix build warnings for make

* Remove meson.build

* Print shift amount in decimal

* Patch non LLVM register alias.

* Change type of immediate operand to unsiged (due to: #771)

* Replace all occurances of a register with its alias.

* Fix printing of signed imms

* Print rotate amount in decimal

* CHange imm type to int64_t to match LLVM imm type.

* Fix search for register names, by completing string first.

* Print ModImm operands always in decimal

* Use number format of previous capstone version.

* Correct implicit writes and update_flags according to SBit.

* Add missing test for RegImmShift

* Reverse incorrect comparision.

* Set shift information for move instructions.

* Set mem access for all memory operands

* Set subtracted flag if offset is negative.

* Add flag for post-index memory operands.

* Add detail op for BX_RET and MOVPCLR

* Use instruction post_index operand.

* Add VPOP and VPUSH as unique CS IDs.

* Add shifting info for MOVsr.

* Add TODOs.

* Add in LLVM hardcoded operands to detail.

* Move detail editing from InstPrinter to Mapping

* Formatting

* Add removed check.

* Add writeback register and constraints to RFEI instructions.

* Translate shift immediate

* Print negative immediates

* Remove duplicate invalid entry

* Add CS groups to instructions

* Fix write attriutes of stores.

* Add missing names of added instructions

* Fix LLVM bug

* Add more post_index flags

* http -> https

* Make generated functions static

* Remove tab prefix for alias instructions.

* Set ValidateMCOperand to NULL.

* Fix AddrMode3Operand operands

* Allow getting system and banked register name via API

* Add writeback to STC/LDC instructions.

* Fix (hopefully) last case where disp is negative and subtracted = true

* Remove accidentially introduced regressions
2023-07-19 17:56:27 +08:00
Rot127
8fefc328b9 Replace strncpy with memcpy to fix compiler warning. 2023-07-05 04:40:32 -05:00
billow
568d179f85 Update tests and inc files
with llvm-capstone 78180b63f827ee38e23375e7a00825e848aa6956
2023-07-01 16:26:54 +08:00
billow
a5bf3841b4 Add # prefix to tricore imm operand 2023-07-01 09:13:14 +08:00
Anton Kochkov
1befcbb723 Convert Tricore to Intel register syntax 2023-06-28 21:48:37 +08:00
Chua Zheng Leong
3c2b407922 Fix access bug for TEST op (#1511)
* Fix access bug for TEST op

Results for TEST instructions are discarded hence operands should have
no write access.

* Fix access bug for TEST (reduce)

* trigger new ci test

---------

Co-authored-by: kabeor <1597915586@qq.com>
2023-06-26 09:21:39 -07:00
Wu ChenXu
2fd6b14dbe Merge pull request #2061 from arkup/next
fix for msvc static lib, dll build error and warnings
2023-06-25 17:33:28 +08:00
Adam Seitz
47c0c91aab Support repz prefix on X86 ret instructions 2023-06-24 09:25:04 -04:00
arkup
e72e161ab0 fix msvc static lib build error 2023-06-23 15:19:33 +02:00
Wu ChenXu
b98189dce9 Merge pull request #2007 from peace-maker/riscv_insn_groups
RISCV: Add call, int and branch_relative instruction groups
2023-06-10 20:08:47 +08:00
Rot127
c0ca4851b9 Hotfix for -DCAPSTONE_DIET build. 2023-05-30 14:17:19 -05:00
Peace-Maker
cb6b9487f9 Merge branch 'next' into riscv_insn_groups 2023-05-30 16:23:34 +02:00
Wu ChenXu
bafd499aae Merge pull request #2034 from imbillow/tc-reg-rw
Add operands access support for TriCore
2023-05-30 21:17:34 +08:00
billow
10a24a9a38 Add operands access support for TriCore 2023-05-30 12:27:38 +08:00
Rot127
9792718a3c Replace strncpy with memcpy because we copy from larger to smaller buffer. 2023-05-27 04:57:10 -05:00
Rot127
b3017894d6 Set mnemonic in PPC_printInst().
Because the cs_insn->mnemonic gets set *after* the
post_printer is called and cs_insn->mnemonic is not memset to 0
before, post_printer() of PPC receives a cs_insn->mnemonic with
random data.
This in turn leads randomly to incorrect setting of the branch hints
and the update_cr0 flag. Because those are set in the post_printer()
of PPC.
2023-05-21 09:55:41 -05:00
billow
06126191e3 Fix compile warning 2023-05-20 19:55:14 +08:00
Wu ChenXu
95fa62d8fa Merge pull request #2022 from stevielavern/fix_pac 2023-05-20 10:19:19 +08:00
Wu ChenXu
7fbfce7aee Merge pull request #2023 from imbillow/tricore_fix
Fix disassemble of `xor`
2023-05-18 15:38:20 +08:00
billow
0fdff8dc33 Fix disassemble of xor
- update generate file using 78180b63f8
2023-05-18 07:29:02 +08:00
stevielavern
8e6b3e4eb3 Fix register accesses & operands of multiple PAC instructions 2023-05-16 14:10:00 +02:00
Wu ChenXu
023afee4f4 Merge pull request #2019 from imbillow/tricore-fix-disp 2023-05-16 10:44:09 +08:00
Wu ChenXu
2d95755bad Merge pull request #2017 from Rot127/fix_sh_warnings 2023-05-16 10:43:40 +08:00
billow
6f44941806 Fix disp fill 2023-05-14 06:34:46 +08:00
Rot127
97290921ac Initialize rw 2023-05-13 03:52:15 -05:00
billow
b19a370f86 Update arch/TriCore/TriCoreInstPrinter.c
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2023-05-13 03:38:27 +08:00
billow
35f151558f Update arch/TriCore/TriCoreInstPrinter.c
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2023-05-13 03:38:21 +08:00
billow
ec19bd9df2 Update arch/TriCore/TriCoreInstPrinter.c
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2023-05-13 03:37:08 +08:00
billow
4ad9cb1b02 Refactor TriCoreInstPrinter.c 2023-05-13 03:01:24 +08:00
billow
44b8610297 Fix tricore disp print 2023-05-13 02:45:00 +08:00
Rot127
c04b436af6 Fix warnings about unhandled switch cases by adding defaults. 2023-05-12 13:40:24 -05:00
billow
b0f9097884 Fix tricore disp24 print 2023-05-13 02:29:26 +08:00
Rot127
d1b97799b5 Update indentation 2023-05-11 11:45:33 -05:00
Rot127
7326053a0b Fix SH build warnings. 2023-05-11 09:15:12 -05:00
billow
404edd5772 Fix compilation warnings related to TriCore. (#2012)
* fix tricore compiler warn `-Wmissing-prototypes`

* include cstool.h
2023-05-09 20:46:10 +08:00
Peace-Maker
7c0d3be0f9 RISCV: add more instruction groups
Add call, ret, int and branch_relative instruction groups to riscv
mappings.
2023-05-01 22:55:26 +02:00
billow
114f1ad867 Upper all inc and fix 2023-05-01 22:52:47 +08:00
billow
c8e5f758a0 Merge branch 'next' into tricore 2023-04-27 13:23:35 +08:00
billow
2873d3b58c Fix tricore.h and remove inc folder 2023-04-25 09:24:07 +08:00
billow
acc8c3fb13 Fix print_insn_detail_tricore and disp fill 2023-04-23 15:14:03 +08:00
billow
2c052afe3c Fix format error 2023-04-23 14:43:14 +08:00
billow
2785d31399 Format all .(c|h) code 2023-04-20 21:55:37 +08:00
billow
2919f94530 fix all tricore compile warnings 2023-04-20 09:22:25 +08:00
billow
26cb58dabc fix: support for TriCore call group mapping 2023-04-20 08:35:13 +08:00
Junghee Lim
4d200beab7 Add handling of prefix NOTRACK 2023-04-19 17:13:39 -04:00
billow
a4118c4ec9 update TriCoreGenAsmWriter.inc 2023-04-14 00:36:16 +08:00
billow
008ef096d3 Update tricore .inc 2023-04-14 00:36:12 +08:00
billow
b412f528c8 fix TriCoreGenCSMappingInsnName.inc 2023-04-14 00:36:11 +08:00