mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-27 15:30:33 +00:00
ef89b18a88
* Update sysop inc file
* Fix missing braces warning
* Handle new system operands
* Fix build errors by renaming.
* Fix segfault
* Fix segfault
* Add custom MCOperand valiadtors
* Add AArch64 case for getFeatureBits
* Fix infinite loop
* Fix braces warning.
* Implement loopuo by name for sys operands
* Fix incorrect translation which remove else if statements.
* Fix several segfaults
* Rename GetRegFromClass patch
* Fix segfaults and asserts
* Fix segfault
* Move MRI setting to Mapping
* Remove unused code
* Add add_op_X functinos for AArch64.
* Add fill detail functins
* Handle RegWithShiftExtend operands
* Handle TypedVectorList operands.
* Handle ComplexRoatation operands
* Handle MemExtend operands
* Handle ImmRangeScale operands
* Handle ExactFPImm operands
* Handle GPRSeqPairsClass operands
* Handle Imm8OptLsl operands
* Handle ImmScale operands
* Handle LogicalImm operands
* Handle Matrix operands
* Handle SME Matrix tiles and vectors.
* Handle normal operands.
* Fix segfault.
* Handle PostInc operands.
* Reorder VecLayout enum to have no duplicate enum value.
* Handle PredicateAsCounter operands
* Handle ZPRasFPR operands
* Handle VectorIndex operands
* Handle UImm12Offset operands.
* Move reg suffix to enum val to single function.
* Handle SVERegOp operands
* Handle SVELogicalImm operands
* Handle SImm operand
* Handle PrefetchOp operands
* Handle Imm and ImmHex operands
* Handle GPR64as32 and GPR64x8 operands
* Add missing break
* Handle FPImm operand
* Handle ExtendedRegister opreand
* Handle CondCode operands
* Handle BTIHintOp operands
* Handle BarrierOption operands
* Handle BarrierXSOption
* Add not implemeted case again
* Handle ArithExtend operands
* Handle AdrpLabel and AlignedLabel operands
* Handle AMNoIndex operands
* Handle AddSubImm operands
* Handle MSRSystemRegisters and MRSSystemRegister operands
* Handle PSBHntOp and RPRFMOperand operands
* Remove unused variables
* Handle InverseCondCode operands
* Handle ImplicityTypedVectorList operands
* Handle ShiftedRegister operands
* Handle Shifter operands
* Handle SIMDType10Operand operands
* Handle SVCROp operands
* Handle SVEPattern operands
* Handle SVEVecLenSpecifier operands
* Handle SysCROperands
* Handle SysXzrPair operands
* Handle PState operands
* Handle VRegOperands
* Primt SME oeprands.
* Fix cs_operand.h include
* Rename arm64 -> aarch64 in python bindings.
* Add Python bindings for SH
* Fix ARM Python bindings (#2127)
* Restructure auto-sync update scripts.
* Move Helper functions to Updater dir
* Move requirements.txt
* Add basic ASUpdater.py
* Run black.
* Add inc file generater to updater
* Add option to select certain inc files fore generation.
* Enable clean build and implement patcher for inc files.
* Format config
* Patch main header files after inc generation.
* Implement clang-format function (unused yet, because it takes forever.)
* Copy generated inc files to arch dir
* Invert clean option (noramlly we need to clean the build dir.)
* Clearify arg doc
* Rename SystemRegister file for AArch64
* Centralize handling of path variables.
* Check if SystemOperands had to be generated before renaming on of its files.
* Replace class parameters by calling get_path
* Remove updater config which only contained paths.
* Add refactor option.
* Remove more path handling in the Configurator.
* Add translation step to updater.
* Fix includes after CppTranslator was moved into the Updater
* Remove updater config
* Fix several issue in the Configurator
* Fix file operations
* Remove addition argument from translator.
* Add Differ step to updater.
* Add path variable for arch_config
* Add diff step.
* Fix typo
* Introduce .clang-format path variable.
* Remove duplicate functions
* Add option to select update steps to execute.
* Check in write functions for write flag.
* Rename PatchMainHeader -> HeaderPatcher
* Move .gitignore
* Add README to vendor dir.
* Add all system operands to cstool output
* Update cstest with aarch64 changes
* Remove wb flag of aarch64 detail struct
* Set updates_flag after decoding
* Set writeback after decoding.
* Rename ARM64 -> AArch64
* Update printer and op mapping
* Exit normally
* Add AArch64 alias
* Fix some tmeplate function calls
* Fix flag check after rebase.
* Fix build by commentig unnused code.
* Add memory operand flag
* Handle memory operands printed via generic printOperand function.
* Handle UImm memory offsets
* Introduce MEM_REG and MEM_IMM op types
* Handle scaled memory immediates
* Check for op_count before checking for mem op at -1 index.
* Update memory operand flags.
* Pass imm/reg memory ops in set_imm/reg to set_mem.
* Add missing set_sme_operand call and fix assert.
* Remove CS_OP_MEM flag before entering switch.
* Preidcates are registers.
* Add shift info always to the previous operand
* Check for generic system regs
* Handle NumLanes = 0 LaneKind = q case
* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.
* Handle FP operands in printOperand.
* Add access information to float operands.
* Rewrite SME matrix handling.
* Set correct SME layouts and allow for immediate range sme offsets.
* Handle cases of unknown system alias by setting their raw values
* Update cstool and header file with new SME offset handling
* Handle SME Tile lists.
* Fix build error in cstest
* Update MC tests for AArch64
* Handle TLBI operands and fix printing bug.
* Fix: Print signed value as signed.
* Add more system alias to detail.
* Remove duplicate hex prefix
* Set correct values for the register info
* Replace tabs with white spaces
* Move string append logic to own function.
* Set DecodeComplete = true before decoding (as originally in the LLVM code).
* Change type of feature argument, since only LLVM features are passed, not CS groups.
* Imitate lower_bound for the index table binary search.
* Remove trailing comments from test files.
* Print shift amount in decimal
* Save detail of shift alias instructions.
* Add extension details fot ext instruction alias
* Print LSB and width in decimal
* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.
* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.
* Fix feature check. Add check for FeatureAll since it includes XS
* Operate on temporary MCInst when trying decoding.
* Add lower_bound behavior to IndexTypeStr binsearch.
* Fix MC tests which were incorrect because of missing FeatureAll check
* Add Alias handling for AArch64
* Update system operands with SYSIMM types and add additional sysop category.
* Add macros for meta programming (ARM64 <-> AArch64 selection).
* Fix union/struct confusion and add raw_value member to uninions.
* Allow to set Syntax and mode options for AArch64
* Fix build warning by using correct type
* Print shift value in decimal
* Add missing call to add_cs_detail.
* Update name map files with normalized names.
* Remove unused function
* Add check if detail should be filled.
* Fill detail for real instructions if only real detail is requested.
* Add always the extension.
* Make dir creation log message debug level
* Implement ADR immediate operand printer.
See: c3484b1fdc
* Check for flag registers beeing written and update flag.
* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.
+ Print CC if it is EQ
* Fix incorrectly initialized CC and VectorLayout.
* Add LSL shift type for extensions.
* Fix case when shift amount is 0
* Fix post-index memory instructions.
* Pass raw immediate through getShiftValue to extract actual shift amount
* Setup AArch64 detail ops.
* Add flag for operands part of a list.
* Set vector indices for all relevant registers.
* Add missing call to add_cs_detail for postIncOperands
* Add ugly yet reliable way to determine post-index addressing mode
* Add support for old Capstone register alias.
* Remove leading space before some alias mnemonics.
* add AARCH64 to `cmake.sh`
* add HAS_AARCH64 to `cs.c`
* should probably just reference `cs_operand.h` in `aarch64.h`
* hint compiler at `AArch64_SYSREG` enum type for casting purposes
* update `Makefile` for AARCH64
leaves `CAPSTONE_HAS_ARM64` supported
* `testFeatureBits` platform function check
`testFeatureBits` should check if the platform function is visible first
* update tests to use AARCH64 convention
* hack: avoid enum casts for `MCInst` Values
Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly
is a hack and needs proper review
* Check for present detail before accessing it.
* Add CS only groups
* Use general map ins_op type
* Fix build warning about str size computation.
* Disable warning about unitialized value for GCC 11.
Imm is initialized and the warning does not appear
in later versions.
* Use correct include guard for PPC
* Add missing requirements
* Update SystemOperand enums.
* Fix overlapping comparison warning
* Fix reachable assert where OpNum is not of type IMM
* Handle 0.0 operand for fcmp
* Fix incorrect variable passed.
* Fix for MacOS which doesn't know the warning and throws another one.
* Make getExtendEncoding static to fix build warning on MSVC.
* Fix build error: 'missing binary operator before token' by checking __GNUC__
* Add string search to add vector layout info.
* Add missing mem disponents of several ldr and str instructions.
* Add 0 immediates to several instructions.
* Rename v regs to q and d variant.
The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.
* Fix incorrect enum value.
* Fix tests for system operands.
* Fix syntax issues in tests.
* Rename Arm64 -> AArch64 Python bindings.
* Fix Python bindings C structs.
* Fix generation of constants (ARMCC skipped because it starts with ARM)
* Update const files
* Remove -Wmaybe-uninitialized warning since it fails fuzz build
* Add missing comma
* Fix case
* Fix AArch64 Python bindings:
- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.
* Rename ARM64 -> AArch64 in test_corpus.py
* Rename test_arm64 -> test_aarch64
* Rename ARM-64 -> AArch64
* Fix diff CI test by disassembling AArch64 at former ARM64 place
* Fix several wrong types and remove unnecessary memebers from Python binding
* Fix: Same printing format of detail for cstool, test_ and test_*.py
* Fix: pass correct op index for mov alias with op[1] == reg wzr.
* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.
* Fix: If barrier ops are not set an assert is reached.
We fix it here by simply getting the immediate as the printing code does.
---------
Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
1688 lines
41 KiB
C
1688 lines
41 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
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#pragma warning(disable:4996) // disable MSVC's warning on strcpy()
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#pragma warning(disable:28719) // disable MSVC's warning on strcpy()
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#endif
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#if defined(CAPSTONE_HAS_OSXKERNEL)
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#include <Availability.h>
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#include <libkern/libkern.h>
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#else
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#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#endif
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#include <string.h>
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#include <capstone/capstone.h>
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#include "utils.h"
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#include "MCRegisterInfo.h"
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#if defined(_KERNEL_MODE)
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#include "windows\winkernel_mm.h"
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#endif
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// Issue #681: Windows kernel does not support formatting float point
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#if defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET)
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#if defined(CAPSTONE_HAS_ARM) || defined(CAPSTONE_HAS_AARCH64) || defined(CAPSTONE_HAS_M68K)
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#define CAPSTONE_STR_INTERNAL(x) #x
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#define CAPSTONE_STR(x) CAPSTONE_STR_INTERNAL(x)
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#define CAPSTONE_MSVC_WRANING_PREFIX __FILE__ "("CAPSTONE_STR(__LINE__)") : warning message : "
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#pragma message(CAPSTONE_MSVC_WRANING_PREFIX "Windows driver does not support full features for selected architecture(s). Define CAPSTONE_DIET to compile Capstone with only supported features. See issue #681 for details.")
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#undef CAPSTONE_MSVC_WRANING_PREFIX
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#undef CAPSTONE_STR
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#undef CAPSTONE_STR_INTERNAL
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#endif
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#endif // defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET)
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#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(CAPSTONE_DIET) && !defined(_KERNEL_MODE)
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#define INSN_CACHE_SIZE 32
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#else
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// reduce stack variable size for kernel/firmware
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#define INSN_CACHE_SIZE 8
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#endif
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// default SKIPDATA mnemonic
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#ifndef CAPSTONE_DIET
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#define SKIPDATA_MNEM ".byte"
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#else // No printing is available in diet mode
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#define SKIPDATA_MNEM NULL
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#endif
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#include "arch/AArch64/AArch64Module.h"
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#include "arch/ARM/ARMModule.h"
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#include "arch/EVM/EVMModule.h"
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#include "arch/WASM/WASMModule.h"
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#include "arch/M680X/M680XModule.h"
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#include "arch/M68K/M68KModule.h"
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#include "arch/Mips/MipsModule.h"
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#include "arch/PowerPC/PPCModule.h"
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#include "arch/Sparc/SparcModule.h"
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#include "arch/SystemZ/SystemZModule.h"
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#include "arch/TMS320C64x/TMS320C64xModule.h"
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#include "arch/X86/X86Module.h"
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#include "arch/XCore/XCoreModule.h"
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#include "arch/RISCV/RISCVModule.h"
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#include "arch/MOS65XX/MOS65XXModule.h"
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#include "arch/BPF/BPFModule.h"
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#include "arch/SH/SHModule.h"
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#include "arch/TriCore/TriCoreModule.h"
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static const struct {
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// constructor initialization
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cs_err (*arch_init)(cs_struct *);
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// support cs_option()
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cs_err (*arch_option)(cs_struct *, cs_opt_type, size_t value);
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// bitmask for finding disallowed modes for an arch:
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// to be called in cs_open()/cs_option()
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cs_mode arch_disallowed_mode_mask;
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} arch_configs[MAX_ARCH] = {
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#ifdef CAPSTONE_HAS_ARM
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{
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ARM_global_init,
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ARM_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_V8 | CS_MODE_MCLASS
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| CS_MODE_THUMB | CS_MODE_BIG_ENDIAN)
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_AARCH64
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{
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AArch64_global_init,
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AArch64_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_MIPS
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{
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Mips_global_init,
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Mips_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO
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| CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MIPS2 | CS_MODE_MIPS3),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_X86
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{
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X86_global_init,
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X86_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_16),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_POWERPC
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{
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PPC_global_init,
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PPC_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_BIG_ENDIAN
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| CS_MODE_QPX | CS_MODE_PS | CS_MODE_BOOKE),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_SPARC
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{
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Sparc_global_init,
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Sparc_option,
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~(CS_MODE_BIG_ENDIAN | CS_MODE_V9),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_SYSZ
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{
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SystemZ_global_init,
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SystemZ_option,
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~(CS_MODE_BIG_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_XCORE
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{
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XCore_global_init,
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XCore_option,
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~(CS_MODE_BIG_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_M68K
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{
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M68K_global_init,
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M68K_option,
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~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_000 | CS_MODE_M68K_010 | CS_MODE_M68K_020
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| CS_MODE_M68K_030 | CS_MODE_M68K_040 | CS_MODE_M68K_060),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_TMS320C64X
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{
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TMS320C64x_global_init,
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TMS320C64x_option,
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~(CS_MODE_BIG_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_M680X
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{
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M680X_global_init,
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M680X_option,
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~(CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | CS_MODE_M680X_6800
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| CS_MODE_M680X_6801 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808
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| CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | CS_MODE_M680X_CPU12
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| CS_MODE_M680X_HCS08),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_EVM
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{
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EVM_global_init,
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EVM_option,
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0,
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_MOS65XX
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{
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MOS65XX_global_init,
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MOS65XX_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_MOS65XX_6502 | CS_MODE_MOS65XX_65C02
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| CS_MODE_MOS65XX_W65C02 | CS_MODE_MOS65XX_65816_LONG_MX),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_WASM
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{
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WASM_global_init,
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WASM_option,
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0,
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_BPF
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{
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BPF_global_init,
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BPF_option,
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~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC | CS_MODE_BPF_EXTENDED
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| CS_MODE_BIG_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_RISCV
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{
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RISCV_global_init,
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RISCV_option,
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~(CS_MODE_RISCV32 | CS_MODE_RISCV64 | CS_MODE_RISCVC),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_SH
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{
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SH_global_init,
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SH_option,
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~(CS_MODE_SH2 | CS_MODE_SH2A | CS_MODE_SH3 |
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CS_MODE_SH4 | CS_MODE_SH4A |
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CS_MODE_SHFPU | CS_MODE_SHDSP|CS_MODE_BIG_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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#ifdef CAPSTONE_HAS_TRICORE
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{
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TRICORE_global_init,
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TRICORE_option,
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~(CS_MODE_TRICORE_110 | CS_MODE_TRICORE_120 | CS_MODE_TRICORE_130
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| CS_MODE_TRICORE_131 | CS_MODE_TRICORE_160 | CS_MODE_TRICORE_161
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| CS_MODE_TRICORE_162 | CS_MODE_LITTLE_ENDIAN),
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},
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#else
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{ NULL, NULL, 0 },
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#endif
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};
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// bitmask of enabled architectures
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static const uint32_t all_arch = 0
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#ifdef CAPSTONE_HAS_ARM
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| (1 << CS_ARCH_ARM)
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#endif
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#if defined(CAPSTONE_HAS_AARCH64) || defined(CAPSTONE_HAS_ARM64)
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| (1 << CS_ARCH_AARCH64)
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#endif
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#ifdef CAPSTONE_HAS_MIPS
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| (1 << CS_ARCH_MIPS)
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#endif
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#ifdef CAPSTONE_HAS_X86
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| (1 << CS_ARCH_X86)
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#endif
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#ifdef CAPSTONE_HAS_POWERPC
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| (1 << CS_ARCH_PPC)
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#endif
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#ifdef CAPSTONE_HAS_SPARC
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| (1 << CS_ARCH_SPARC)
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#endif
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#ifdef CAPSTONE_HAS_SYSZ
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| (1 << CS_ARCH_SYSZ)
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#endif
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#ifdef CAPSTONE_HAS_XCORE
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| (1 << CS_ARCH_XCORE)
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#endif
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#ifdef CAPSTONE_HAS_M68K
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| (1 << CS_ARCH_M68K)
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#endif
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#ifdef CAPSTONE_HAS_TMS320C64X
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| (1 << CS_ARCH_TMS320C64X)
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#endif
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#ifdef CAPSTONE_HAS_M680X
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| (1 << CS_ARCH_M680X)
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#endif
|
|
#ifdef CAPSTONE_HAS_EVM
|
|
| (1 << CS_ARCH_EVM)
|
|
#endif
|
|
#ifdef CAPSTONE_HAS_MOS65XX
|
|
| (1 << CS_ARCH_MOS65XX)
|
|
#endif
|
|
#ifdef CAPSTONE_HAS_WASM
|
|
| (1 << CS_ARCH_WASM)
|
|
#endif
|
|
#ifdef CAPSTONE_HAS_BPF
|
|
| (1 << CS_ARCH_BPF)
|
|
#endif
|
|
#ifdef CAPSTONE_HAS_RISCV
|
|
| (1 << CS_ARCH_RISCV)
|
|
#endif
|
|
#ifdef CAPSTONE_HAS_SH
|
|
| (1 << CS_ARCH_SH)
|
|
#endif
|
|
#ifdef CAPSTONE_HAS_TRICORE
|
|
| (1 << CS_ARCH_TRICORE)
|
|
#endif
|
|
;
|
|
|
|
|
|
#if defined(CAPSTONE_USE_SYS_DYN_MEM)
|
|
#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE)
|
|
// default
|
|
cs_malloc_t cs_mem_malloc = malloc;
|
|
cs_calloc_t cs_mem_calloc = calloc;
|
|
cs_realloc_t cs_mem_realloc = realloc;
|
|
cs_free_t cs_mem_free = free;
|
|
#if defined(_WIN32_WCE)
|
|
cs_vsnprintf_t cs_vsnprintf = _vsnprintf;
|
|
#else
|
|
cs_vsnprintf_t cs_vsnprintf = vsnprintf;
|
|
#endif // defined(_WIN32_WCE)
|
|
|
|
#elif defined(_KERNEL_MODE)
|
|
// Windows driver
|
|
cs_malloc_t cs_mem_malloc = cs_winkernel_malloc;
|
|
cs_calloc_t cs_mem_calloc = cs_winkernel_calloc;
|
|
cs_realloc_t cs_mem_realloc = cs_winkernel_realloc;
|
|
cs_free_t cs_mem_free = cs_winkernel_free;
|
|
cs_vsnprintf_t cs_vsnprintf = cs_winkernel_vsnprintf;
|
|
#else
|
|
// OSX kernel
|
|
extern void* kern_os_malloc(size_t size);
|
|
extern void kern_os_free(void* addr);
|
|
extern void* kern_os_realloc(void* addr, size_t nsize);
|
|
|
|
static void* cs_kern_os_calloc(size_t num, size_t size)
|
|
{
|
|
return kern_os_malloc(num * size); // malloc bzeroes the buffer
|
|
}
|
|
|
|
cs_malloc_t cs_mem_malloc = kern_os_malloc;
|
|
cs_calloc_t cs_mem_calloc = cs_kern_os_calloc;
|
|
cs_realloc_t cs_mem_realloc = kern_os_realloc;
|
|
cs_free_t cs_mem_free = kern_os_free;
|
|
cs_vsnprintf_t cs_vsnprintf = vsnprintf;
|
|
#endif // !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE)
|
|
#else
|
|
// User-defined
|
|
cs_malloc_t cs_mem_malloc = NULL;
|
|
cs_calloc_t cs_mem_calloc = NULL;
|
|
cs_realloc_t cs_mem_realloc = NULL;
|
|
cs_free_t cs_mem_free = NULL;
|
|
cs_vsnprintf_t cs_vsnprintf = NULL;
|
|
|
|
#endif // defined(CAPSTONE_USE_SYS_DYN_MEM)
|
|
|
|
CAPSTONE_EXPORT
|
|
unsigned int CAPSTONE_API cs_version(int *major, int *minor)
|
|
{
|
|
if (major != NULL && minor != NULL) {
|
|
*major = CS_API_MAJOR;
|
|
*minor = CS_API_MINOR;
|
|
}
|
|
|
|
return (CS_API_MAJOR << 8) + CS_API_MINOR;
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
bool CAPSTONE_API cs_support(int query)
|
|
{
|
|
if (query == CS_ARCH_ALL)
|
|
return all_arch ==
|
|
((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) |
|
|
(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
|
|
(1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) |
|
|
(1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE) |
|
|
(1 << CS_ARCH_M68K) | (1 << CS_ARCH_TMS320C64X) |
|
|
(1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM) |
|
|
(1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) |
|
|
(1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) |
|
|
(1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE));
|
|
|
|
if ((unsigned int)query < CS_ARCH_MAX)
|
|
return all_arch & (1 << query);
|
|
|
|
if (query == CS_SUPPORT_DIET) {
|
|
#ifdef CAPSTONE_DIET
|
|
return true;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
if (query == CS_SUPPORT_X86_REDUCE) {
|
|
#if defined(CAPSTONE_HAS_X86) && defined(CAPSTONE_X86_REDUCE)
|
|
return true;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
// unsupported query
|
|
return false;
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
cs_err CAPSTONE_API cs_errno(csh handle)
|
|
{
|
|
struct cs_struct *ud;
|
|
if (!handle)
|
|
return CS_ERR_CSH;
|
|
|
|
ud = (struct cs_struct *)(uintptr_t)handle;
|
|
|
|
return ud->errnum;
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
const char * CAPSTONE_API cs_strerror(cs_err code)
|
|
{
|
|
switch(code) {
|
|
default:
|
|
return "Unknown error code";
|
|
case CS_ERR_OK:
|
|
return "OK (CS_ERR_OK)";
|
|
case CS_ERR_MEM:
|
|
return "Out of memory (CS_ERR_MEM)";
|
|
case CS_ERR_ARCH:
|
|
return "Invalid/unsupported architecture(CS_ERR_ARCH)";
|
|
case CS_ERR_HANDLE:
|
|
return "Invalid handle (CS_ERR_HANDLE)";
|
|
case CS_ERR_CSH:
|
|
return "Invalid csh (CS_ERR_CSH)";
|
|
case CS_ERR_MODE:
|
|
return "Invalid mode (CS_ERR_MODE)";
|
|
case CS_ERR_OPTION:
|
|
return "Invalid option (CS_ERR_OPTION)";
|
|
case CS_ERR_DETAIL:
|
|
return "Details are unavailable (CS_ERR_DETAIL)";
|
|
case CS_ERR_MEMSETUP:
|
|
return "Dynamic memory management uninitialized (CS_ERR_MEMSETUP)";
|
|
case CS_ERR_VERSION:
|
|
return "Different API version between core & binding (CS_ERR_VERSION)";
|
|
case CS_ERR_DIET:
|
|
return "Information irrelevant in diet engine (CS_ERR_DIET)";
|
|
case CS_ERR_SKIPDATA:
|
|
return "Information irrelevant for 'data' instruction in SKIPDATA mode (CS_ERR_SKIPDATA)";
|
|
case CS_ERR_X86_ATT:
|
|
return "AT&T syntax is unavailable (CS_ERR_X86_ATT)";
|
|
case CS_ERR_X86_INTEL:
|
|
return "INTEL syntax is unavailable (CS_ERR_X86_INTEL)";
|
|
case CS_ERR_X86_MASM:
|
|
return "MASM syntax is unavailable (CS_ERR_X86_MASM)";
|
|
}
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
|
|
{
|
|
cs_err err;
|
|
struct cs_struct *ud;
|
|
if (!cs_mem_malloc || !cs_mem_calloc || !cs_mem_realloc || !cs_mem_free || !cs_vsnprintf)
|
|
// Error: before cs_open(), dynamic memory management must be initialized
|
|
// with cs_option(CS_OPT_MEM)
|
|
return CS_ERR_MEMSETUP;
|
|
|
|
if (arch < CS_ARCH_MAX && arch_configs[arch].arch_init) {
|
|
// verify if requested mode is valid
|
|
if (mode & arch_configs[arch].arch_disallowed_mode_mask) {
|
|
*handle = 0;
|
|
return CS_ERR_MODE;
|
|
}
|
|
|
|
ud = cs_mem_calloc(1, sizeof(*ud));
|
|
if (!ud) {
|
|
// memory insufficient
|
|
return CS_ERR_MEM;
|
|
}
|
|
|
|
ud->errnum = CS_ERR_OK;
|
|
ud->arch = arch;
|
|
ud->mode = mode;
|
|
// by default, do not break instruction into details
|
|
ud->detail_opt = CS_OPT_OFF;
|
|
|
|
// default skipdata setup
|
|
ud->skipdata_setup.mnemonic = SKIPDATA_MNEM;
|
|
|
|
err = arch_configs[ud->arch].arch_init(ud);
|
|
if (err) {
|
|
cs_mem_free(ud);
|
|
*handle = 0;
|
|
return err;
|
|
}
|
|
|
|
*handle = (uintptr_t)ud;
|
|
|
|
return CS_ERR_OK;
|
|
} else {
|
|
*handle = 0;
|
|
return CS_ERR_ARCH;
|
|
}
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
cs_err CAPSTONE_API cs_close(csh *handle)
|
|
{
|
|
struct cs_struct *ud;
|
|
struct insn_mnem *next, *tmp;
|
|
|
|
if (*handle == 0)
|
|
// invalid handle
|
|
return CS_ERR_CSH;
|
|
|
|
ud = (struct cs_struct *)(*handle);
|
|
|
|
if (ud->printer_info)
|
|
cs_mem_free(ud->printer_info);
|
|
|
|
// free the linked list of customized mnemonic
|
|
tmp = ud->mnem_list;
|
|
while(tmp) {
|
|
next = tmp->next;
|
|
cs_mem_free(tmp);
|
|
tmp = next;
|
|
}
|
|
|
|
cs_mem_free(ud->insn_cache);
|
|
|
|
memset(ud, 0, sizeof(*ud));
|
|
cs_mem_free(ud);
|
|
|
|
// invalidate this handle by ZERO out its value.
|
|
// this is to make sure it is unusable after cs_close()
|
|
*handle = 0;
|
|
|
|
return CS_ERR_OK;
|
|
}
|
|
|
|
// replace str1 in target with str2; target starts with str1
|
|
// output is put into result (which is array of char with size CS_MNEMONIC_SIZE)
|
|
// return 0 on success, -1 on failure
|
|
static int str_replace(char *result, char *target, const char *str1, char *str2)
|
|
{
|
|
// only perform replacement if the output fits into result
|
|
if (strlen(target) - strlen(str1) + strlen(str2) < CS_MNEMONIC_SIZE - 1) {
|
|
// copy str2 to begining of result
|
|
strcpy(result, str2);
|
|
// skip str1 - already replaced by str2
|
|
strcat(result, target + strlen(str1));
|
|
|
|
return 0;
|
|
} else
|
|
return -1;
|
|
}
|
|
|
|
/// The asm string sometimes has a leading space or tab.
|
|
/// Here we remove it.
|
|
static void fixup_asm_string(char *asm_str) {
|
|
if (!asm_str) {
|
|
return;
|
|
}
|
|
int i = 0;
|
|
int k = 0;
|
|
bool text_reached = (asm_str[0] != ' ' && asm_str[0] != '\t');
|
|
while (asm_str[i]) {
|
|
if (!text_reached && (asm_str[i] == ' ' || asm_str[i] == '\t')) {
|
|
++i;
|
|
text_reached = true;
|
|
continue;
|
|
}
|
|
asm_str[k] = asm_str[i];
|
|
++k, ++i;
|
|
}
|
|
asm_str[k] = '\0';
|
|
}
|
|
|
|
// fill insn with mnemonic & operands info
|
|
static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci,
|
|
PostPrinter_t postprinter, const uint8_t *code)
|
|
{
|
|
#ifndef CAPSTONE_DIET
|
|
char *sp, *mnem;
|
|
#endif
|
|
fixup_asm_string(buffer);
|
|
uint16_t copy_size = MIN(sizeof(insn->bytes), insn->size);
|
|
|
|
// fill the instruction bytes.
|
|
// we might skip some redundant bytes in front in the case of X86
|
|
memcpy(insn->bytes, code + insn->size - copy_size, copy_size);
|
|
insn->op_str[0] = '\0';
|
|
insn->size = copy_size;
|
|
|
|
// alias instruction might have ID saved in OpcodePub
|
|
if (MCInst_getOpcodePub(mci))
|
|
insn->id = MCInst_getOpcodePub(mci);
|
|
|
|
// post printer handles some corner cases (hacky)
|
|
if (postprinter)
|
|
postprinter((csh)handle, insn, buffer, mci);
|
|
|
|
#ifndef CAPSTONE_DIET
|
|
mnem = insn->mnemonic;
|
|
// memset(mnem, 0, CS_MNEMONIC_SIZE);
|
|
for (sp = buffer; *sp; sp++) {
|
|
if (*sp == ' '|| *sp == '\t')
|
|
break;
|
|
if (*sp == '|') // lock|rep prefix for x86
|
|
*sp = ' ';
|
|
// copy to @mnemonic
|
|
*mnem = *sp;
|
|
mnem++;
|
|
}
|
|
|
|
*mnem = '\0';
|
|
|
|
// we might have customized mnemonic
|
|
if (handle->mnem_list) {
|
|
struct insn_mnem *tmp = handle->mnem_list;
|
|
while(tmp) {
|
|
if (tmp->insn.id == insn->id) {
|
|
char str[CS_MNEMONIC_SIZE];
|
|
|
|
if (!str_replace(str, insn->mnemonic, cs_insn_name((csh)handle, insn->id), tmp->insn.mnemonic)) {
|
|
// copy result to mnemonic
|
|
(void)strncpy(insn->mnemonic, str, sizeof(insn->mnemonic) - 1);
|
|
insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0';
|
|
}
|
|
|
|
break;
|
|
}
|
|
tmp = tmp->next;
|
|
}
|
|
}
|
|
|
|
// copy @op_str
|
|
if (*sp) {
|
|
// find the next non-space char
|
|
sp++;
|
|
for (; ((*sp == ' ') || (*sp == '\t')); sp++);
|
|
strncpy(insn->op_str, sp, sizeof(insn->op_str) - 1);
|
|
insn->op_str[sizeof(insn->op_str) - 1] = '\0';
|
|
} else
|
|
insn->op_str[0] = '\0';
|
|
|
|
#endif
|
|
}
|
|
|
|
// how many bytes will we skip when encountering data (CS_OPT_SKIPDATA)?
|
|
// this very much depends on instruction alignment requirement of each arch.
|
|
static uint8_t skipdata_size(cs_struct *handle)
|
|
{
|
|
switch(handle->arch) {
|
|
default:
|
|
// should never reach
|
|
return (uint8_t)-1;
|
|
case CS_ARCH_ARM:
|
|
// skip 2 bytes on Thumb mode.
|
|
if (handle->mode & CS_MODE_THUMB)
|
|
return 2;
|
|
// otherwise, skip 4 bytes
|
|
return 4;
|
|
case CS_ARCH_AARCH64:
|
|
case CS_ARCH_MIPS:
|
|
case CS_ARCH_PPC:
|
|
case CS_ARCH_SPARC:
|
|
// skip 4 bytes
|
|
return 4;
|
|
case CS_ARCH_SYSZ:
|
|
// SystemZ instruction's length can be 2, 4 or 6 bytes,
|
|
// so we just skip 2 bytes
|
|
return 2;
|
|
case CS_ARCH_X86:
|
|
// X86 has no restriction on instruction alignment
|
|
return 1;
|
|
case CS_ARCH_XCORE:
|
|
// XCore instruction's length can be 2 or 4 bytes,
|
|
// so we just skip 2 bytes
|
|
return 2;
|
|
case CS_ARCH_M68K:
|
|
// M68K has 2 bytes instruction alignment but contain multibyte instruction so we skip 2 bytes
|
|
return 2;
|
|
case CS_ARCH_TMS320C64X:
|
|
// TMS320C64x alignment is 4.
|
|
return 4;
|
|
case CS_ARCH_M680X:
|
|
// M680X alignment is 1.
|
|
return 1;
|
|
case CS_ARCH_EVM:
|
|
// EVM alignment is 1.
|
|
return 1;
|
|
case CS_ARCH_WASM:
|
|
//WASM alignment is 1
|
|
return 1;
|
|
case CS_ARCH_MOS65XX:
|
|
// MOS65XX alignment is 1.
|
|
return 1;
|
|
case CS_ARCH_BPF:
|
|
// both classic and extended BPF have alignment 8.
|
|
return 8;
|
|
case CS_ARCH_RISCV:
|
|
// special compress mode
|
|
if (handle->mode & CS_MODE_RISCVC)
|
|
return 2;
|
|
return 4;
|
|
case CS_ARCH_SH:
|
|
return 2;
|
|
case CS_ARCH_TRICORE:
|
|
// TriCore instruction's length can be 2 or 4 bytes,
|
|
// so we just skip 2 bytes
|
|
return 2;
|
|
}
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
|
|
{
|
|
struct cs_struct *handle;
|
|
cs_opt_mnem *opt;
|
|
|
|
// cs_option() can be called with NULL handle just for CS_OPT_MEM
|
|
// This is supposed to be executed before all other APIs (even cs_open())
|
|
if (type == CS_OPT_MEM) {
|
|
cs_opt_mem *mem = (cs_opt_mem *)value;
|
|
|
|
cs_mem_malloc = mem->malloc;
|
|
cs_mem_calloc = mem->calloc;
|
|
cs_mem_realloc = mem->realloc;
|
|
cs_mem_free = mem->free;
|
|
cs_vsnprintf = mem->vsnprintf;
|
|
|
|
return CS_ERR_OK;
|
|
}
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
if (!handle)
|
|
return CS_ERR_CSH;
|
|
|
|
switch(type) {
|
|
default:
|
|
break;
|
|
|
|
case CS_OPT_UNSIGNED:
|
|
handle->imm_unsigned = (cs_opt_value)value;
|
|
return CS_ERR_OK;
|
|
|
|
case CS_OPT_DETAIL:
|
|
handle->detail_opt |= (cs_opt_value)value;
|
|
return CS_ERR_OK;
|
|
|
|
case CS_OPT_SKIPDATA:
|
|
handle->skipdata = (value == CS_OPT_ON);
|
|
if (handle->skipdata) {
|
|
if (handle->skipdata_size == 0) {
|
|
// set the default skipdata size
|
|
handle->skipdata_size = skipdata_size(handle);
|
|
}
|
|
}
|
|
return CS_ERR_OK;
|
|
|
|
case CS_OPT_SKIPDATA_SETUP:
|
|
if (value) {
|
|
handle->skipdata_setup = *((cs_opt_skipdata *)value);
|
|
if (handle->skipdata_setup.mnemonic == NULL) {
|
|
handle->skipdata_setup.mnemonic = SKIPDATA_MNEM;
|
|
}
|
|
}
|
|
return CS_ERR_OK;
|
|
|
|
case CS_OPT_MNEMONIC:
|
|
opt = (cs_opt_mnem *)value;
|
|
if (opt->id) {
|
|
if (opt->mnemonic) {
|
|
struct insn_mnem *tmp;
|
|
|
|
// add new instruction, or replace existing instruction
|
|
// 1. find if we already had this insn in the linked list
|
|
tmp = handle->mnem_list;
|
|
while(tmp) {
|
|
if (tmp->insn.id == opt->id) {
|
|
// found this instruction, so replace its mnemonic
|
|
(void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1);
|
|
tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0';
|
|
break;
|
|
}
|
|
tmp = tmp->next;
|
|
}
|
|
|
|
// 2. add this instruction if we have not had it yet
|
|
if (!tmp) {
|
|
tmp = cs_mem_malloc(sizeof(*tmp));
|
|
tmp->insn.id = opt->id;
|
|
(void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1);
|
|
tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0';
|
|
// this new instruction is heading the list
|
|
tmp->next = handle->mnem_list;
|
|
handle->mnem_list = tmp;
|
|
}
|
|
return CS_ERR_OK;
|
|
} else {
|
|
struct insn_mnem *prev, *tmp;
|
|
|
|
// we want to delete an existing instruction
|
|
// iterate the list to find the instruction to remove it
|
|
tmp = handle->mnem_list;
|
|
prev = tmp;
|
|
while(tmp) {
|
|
if (tmp->insn.id == opt->id) {
|
|
// delete this instruction
|
|
if (tmp == prev) {
|
|
// head of the list
|
|
handle->mnem_list = tmp->next;
|
|
} else {
|
|
prev->next = tmp->next;
|
|
}
|
|
cs_mem_free(tmp);
|
|
break;
|
|
}
|
|
prev = tmp;
|
|
tmp = tmp->next;
|
|
}
|
|
}
|
|
}
|
|
return CS_ERR_OK;
|
|
|
|
case CS_OPT_MODE:
|
|
// verify if requested mode is valid
|
|
if (value & arch_configs[handle->arch].arch_disallowed_mode_mask) {
|
|
return CS_ERR_OPTION;
|
|
}
|
|
break;
|
|
case CS_OPT_NO_BRANCH_OFFSET:
|
|
if (handle->PrintBranchImmNotAsAddress)
|
|
return CS_ERR_OK;
|
|
break;
|
|
}
|
|
|
|
return arch_configs[handle->arch].arch_option(handle, type, value);
|
|
}
|
|
|
|
// generate @op_str for data instruction of SKIPDATA
|
|
#ifndef CAPSTONE_DIET
|
|
static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size)
|
|
{
|
|
char *p = opstr;
|
|
int len;
|
|
size_t i;
|
|
size_t available = sizeof(((cs_insn*)NULL)->op_str);
|
|
|
|
if (!size) {
|
|
opstr[0] = '\0';
|
|
return;
|
|
}
|
|
|
|
len = cs_snprintf(p, available, "0x%02x", buffer[0]);
|
|
p+= len;
|
|
available -= len;
|
|
|
|
for(i = 1; i < size; i++) {
|
|
len = cs_snprintf(p, available, ", 0x%02x", buffer[i]);
|
|
if (len < 0) {
|
|
break;
|
|
}
|
|
if ((size_t)len > available - 1) {
|
|
break;
|
|
}
|
|
p+= len;
|
|
available -= len;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// dynamicly allocate memory to contain disasm insn
|
|
// NOTE: caller must free() the allocated memory itself to avoid memory leaking
|
|
CAPSTONE_EXPORT
|
|
size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
|
|
{
|
|
struct cs_struct *handle;
|
|
MCInst mci;
|
|
uint16_t insn_size;
|
|
size_t c = 0, i;
|
|
unsigned int f = 0; // index of the next instruction in the cache
|
|
cs_insn *insn_cache; // cache contains disassembled instructions
|
|
void *total = NULL;
|
|
size_t total_size = 0; // total size of output buffer containing all insns
|
|
bool r;
|
|
void *tmp;
|
|
size_t skipdata_bytes;
|
|
uint64_t offset_org; // save all the original info of the buffer
|
|
size_t size_org;
|
|
const uint8_t *buffer_org;
|
|
unsigned int cache_size = INSN_CACHE_SIZE;
|
|
size_t next_offset;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
if (!handle) {
|
|
// FIXME: how to handle this case:
|
|
// handle->errnum = CS_ERR_HANDLE;
|
|
return 0;
|
|
}
|
|
|
|
handle->errnum = CS_ERR_OK;
|
|
|
|
#ifdef CAPSTONE_USE_SYS_DYN_MEM
|
|
if (count > 0 && count <= INSN_CACHE_SIZE)
|
|
cache_size = (unsigned int) count;
|
|
#endif
|
|
|
|
// save the original offset for SKIPDATA
|
|
buffer_org = buffer;
|
|
offset_org = offset;
|
|
size_org = size;
|
|
|
|
total_size = sizeof(cs_insn) * cache_size;
|
|
total = cs_mem_calloc(sizeof(cs_insn), cache_size);
|
|
if (total == NULL) {
|
|
// insufficient memory
|
|
handle->errnum = CS_ERR_MEM;
|
|
return 0;
|
|
}
|
|
|
|
insn_cache = total;
|
|
|
|
while (size > 0) {
|
|
MCInst_Init(&mci);
|
|
mci.csh = handle;
|
|
|
|
// relative branches need to know the address & size of current insn
|
|
mci.address = offset;
|
|
|
|
if (handle->detail_opt) {
|
|
// allocate memory for @detail pointer
|
|
insn_cache->detail = cs_mem_malloc(sizeof(cs_detail));
|
|
} else {
|
|
insn_cache->detail = NULL;
|
|
}
|
|
|
|
// save all the information for non-detailed mode
|
|
mci.flat_insn = insn_cache;
|
|
mci.flat_insn->address = offset;
|
|
#ifdef CAPSTONE_DIET
|
|
// zero out mnemonic & op_str
|
|
mci.flat_insn->mnemonic[0] = '\0';
|
|
mci.flat_insn->op_str[0] = '\0';
|
|
#endif
|
|
|
|
r = handle->disasm(ud, buffer, size, &mci, &insn_size, offset, handle->getinsn_info);
|
|
if (r) {
|
|
SStream ss;
|
|
SStream_Init(&ss);
|
|
|
|
mci.flat_insn->size = insn_size;
|
|
|
|
// map internal instruction opcode to public insn ID
|
|
|
|
handle->insn_id(handle, insn_cache, mci.Opcode);
|
|
|
|
handle->printer(&mci, &ss, handle->printer_info);
|
|
fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer);
|
|
|
|
// adjust for pseudo opcode (X86)
|
|
if (handle->arch == CS_ARCH_X86)
|
|
insn_cache->id += mci.popcode_adjust;
|
|
|
|
next_offset = insn_size;
|
|
} else {
|
|
// encounter a broken instruction
|
|
|
|
// free memory of @detail pointer
|
|
if (handle->detail_opt) {
|
|
cs_mem_free(insn_cache->detail);
|
|
}
|
|
|
|
// if there is no request to skip data, or remaining data is too small,
|
|
// then bail out
|
|
if (!handle->skipdata || handle->skipdata_size > size)
|
|
break;
|
|
|
|
if (handle->skipdata_setup.callback) {
|
|
skipdata_bytes = handle->skipdata_setup.callback(buffer_org, size_org,
|
|
(size_t)(offset - offset_org), handle->skipdata_setup.user_data);
|
|
if (skipdata_bytes > size)
|
|
// remaining data is not enough
|
|
break;
|
|
|
|
if (!skipdata_bytes)
|
|
// user requested not to skip data, so bail out
|
|
break;
|
|
} else
|
|
skipdata_bytes = handle->skipdata_size;
|
|
|
|
// we have to skip some amount of data, depending on arch & mode
|
|
insn_cache->id = 0; // invalid ID for this "data" instruction
|
|
insn_cache->address = offset;
|
|
insn_cache->size = (uint16_t)skipdata_bytes;
|
|
memcpy(insn_cache->bytes, buffer, skipdata_bytes);
|
|
#ifdef CAPSTONE_DIET
|
|
insn_cache->mnemonic[0] = '\0';
|
|
insn_cache->op_str[0] = '\0';
|
|
#else
|
|
strncpy(insn_cache->mnemonic, handle->skipdata_setup.mnemonic,
|
|
sizeof(insn_cache->mnemonic) - 1);
|
|
skipdata_opstr(insn_cache->op_str, buffer, skipdata_bytes);
|
|
#endif
|
|
insn_cache->detail = NULL;
|
|
|
|
next_offset = skipdata_bytes;
|
|
}
|
|
|
|
// one more instruction entering the cache
|
|
f++;
|
|
|
|
// one more instruction disassembled
|
|
c++;
|
|
if (count > 0 && c == count)
|
|
// already got requested number of instructions
|
|
break;
|
|
|
|
if (f == cache_size) {
|
|
// full cache, so expand the cache to contain incoming insns
|
|
cache_size = cache_size * 8 / 5; // * 1.6 ~ golden ratio
|
|
total_size += (sizeof(cs_insn) * cache_size);
|
|
tmp = cs_mem_realloc(total, total_size);
|
|
if (tmp == NULL) { // insufficient memory
|
|
if (handle->detail_opt) {
|
|
insn_cache = (cs_insn *)total;
|
|
for (i = 0; i < c; i++, insn_cache++)
|
|
cs_mem_free(insn_cache->detail);
|
|
}
|
|
|
|
cs_mem_free(total);
|
|
*insn = NULL;
|
|
handle->errnum = CS_ERR_MEM;
|
|
return 0;
|
|
}
|
|
|
|
total = tmp;
|
|
// continue to fill in the cache after the last instruction
|
|
insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c);
|
|
|
|
// reset f back to 0, so we fill in the cache from begining
|
|
f = 0;
|
|
} else
|
|
insn_cache++;
|
|
|
|
buffer += next_offset;
|
|
size -= next_offset;
|
|
offset += next_offset;
|
|
}
|
|
|
|
if (!c) {
|
|
// we did not disassemble any instruction
|
|
cs_mem_free(total);
|
|
total = NULL;
|
|
} else if (f != cache_size) {
|
|
// total did not fully use the last cache, so downsize it
|
|
tmp = cs_mem_realloc(total, total_size - (cache_size - f) * sizeof(*insn_cache));
|
|
if (tmp == NULL) { // insufficient memory
|
|
// free all detail pointers
|
|
if (handle->detail_opt) {
|
|
insn_cache = (cs_insn *)total;
|
|
for (i = 0; i < c; i++, insn_cache++)
|
|
cs_mem_free(insn_cache->detail);
|
|
}
|
|
|
|
cs_mem_free(total);
|
|
*insn = NULL;
|
|
|
|
handle->errnum = CS_ERR_MEM;
|
|
return 0;
|
|
}
|
|
|
|
total = tmp;
|
|
}
|
|
|
|
*insn = total;
|
|
|
|
return c;
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
|
|
{
|
|
size_t i;
|
|
|
|
// free all detail pointers
|
|
for (i = 0; i < count; i++)
|
|
cs_mem_free(insn[i].detail);
|
|
|
|
// then free pointer to cs_insn array
|
|
cs_mem_free(insn);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
cs_insn * CAPSTONE_API cs_malloc(csh ud)
|
|
{
|
|
cs_insn *insn;
|
|
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
insn = cs_mem_malloc(sizeof(cs_insn));
|
|
if (!insn) {
|
|
// insufficient memory
|
|
handle->errnum = CS_ERR_MEM;
|
|
return NULL;
|
|
} else {
|
|
if (handle->detail_opt) {
|
|
// allocate memory for @detail pointer
|
|
insn->detail = cs_mem_malloc(sizeof(cs_detail));
|
|
if (insn->detail == NULL) { // insufficient memory
|
|
cs_mem_free(insn);
|
|
handle->errnum = CS_ERR_MEM;
|
|
return NULL;
|
|
}
|
|
} else
|
|
insn->detail = NULL;
|
|
}
|
|
|
|
return insn;
|
|
}
|
|
|
|
// iterator for instruction "single-stepping"
|
|
CAPSTONE_EXPORT
|
|
bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size,
|
|
uint64_t *address, cs_insn *insn)
|
|
{
|
|
struct cs_struct *handle;
|
|
uint16_t insn_size;
|
|
MCInst mci;
|
|
bool r;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
if (!handle) {
|
|
return false;
|
|
}
|
|
|
|
handle->errnum = CS_ERR_OK;
|
|
|
|
MCInst_Init(&mci);
|
|
mci.csh = handle;
|
|
|
|
// relative branches need to know the address & size of current insn
|
|
mci.address = *address;
|
|
|
|
// save all the information for non-detailed mode
|
|
mci.flat_insn = insn;
|
|
mci.flat_insn->address = *address;
|
|
#ifdef CAPSTONE_DIET
|
|
// zero out mnemonic & op_str
|
|
mci.flat_insn->mnemonic[0] = '\0';
|
|
mci.flat_insn->op_str[0] = '\0';
|
|
#endif
|
|
|
|
r = handle->disasm(ud, *code, *size, &mci, &insn_size, *address, handle->getinsn_info);
|
|
if (r) {
|
|
SStream ss;
|
|
SStream_Init(&ss);
|
|
|
|
mci.flat_insn->size = insn_size;
|
|
|
|
// map internal instruction opcode to public insn ID
|
|
handle->insn_id(handle, insn, mci.Opcode);
|
|
|
|
handle->printer(&mci, &ss, handle->printer_info);
|
|
|
|
fill_insn(handle, insn, ss.buffer, &mci, handle->post_printer, *code);
|
|
|
|
// adjust for pseudo opcode (X86)
|
|
if (handle->arch == CS_ARCH_X86)
|
|
insn->id += mci.popcode_adjust;
|
|
|
|
*code += insn_size;
|
|
*size -= insn_size;
|
|
*address += insn_size;
|
|
} else { // encounter a broken instruction
|
|
size_t skipdata_bytes;
|
|
|
|
// if there is no request to skip data, or remaining data is too small,
|
|
// then bail out
|
|
if (!handle->skipdata || handle->skipdata_size > *size)
|
|
return false;
|
|
|
|
if (handle->skipdata_setup.callback) {
|
|
skipdata_bytes = handle->skipdata_setup.callback(*code, *size,
|
|
0, handle->skipdata_setup.user_data);
|
|
if (skipdata_bytes > *size)
|
|
// remaining data is not enough
|
|
return false;
|
|
|
|
if (!skipdata_bytes)
|
|
// user requested not to skip data, so bail out
|
|
return false;
|
|
} else
|
|
skipdata_bytes = handle->skipdata_size;
|
|
|
|
// we have to skip some amount of data, depending on arch & mode
|
|
insn->id = 0; // invalid ID for this "data" instruction
|
|
insn->address = *address;
|
|
insn->size = (uint16_t)skipdata_bytes;
|
|
#ifdef CAPSTONE_DIET
|
|
insn->mnemonic[0] = '\0';
|
|
insn->op_str[0] = '\0';
|
|
#else
|
|
memcpy(insn->bytes, *code, skipdata_bytes);
|
|
strncpy(insn->mnemonic, handle->skipdata_setup.mnemonic,
|
|
sizeof(insn->mnemonic) - 1);
|
|
skipdata_opstr(insn->op_str, *code, skipdata_bytes);
|
|
#endif
|
|
|
|
*code += skipdata_bytes;
|
|
*size -= skipdata_bytes;
|
|
*address += skipdata_bytes;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// return friendly name of register in a string
|
|
CAPSTONE_EXPORT
|
|
const char * CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
|
|
{
|
|
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle || handle->reg_name == NULL) {
|
|
return NULL;
|
|
}
|
|
|
|
return handle->reg_name(ud, reg);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
const char * CAPSTONE_API cs_insn_name(csh ud, unsigned int insn)
|
|
{
|
|
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle || handle->insn_name == NULL) {
|
|
return NULL;
|
|
}
|
|
|
|
return handle->insn_name(ud, insn);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
const char * CAPSTONE_API cs_group_name(csh ud, unsigned int group)
|
|
{
|
|
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle || handle->group_name == NULL) {
|
|
return NULL;
|
|
}
|
|
|
|
return handle->group_name(ud, group);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
bool CAPSTONE_API cs_insn_group(csh ud, const cs_insn *insn, unsigned int group_id)
|
|
{
|
|
struct cs_struct *handle;
|
|
if (!ud)
|
|
return false;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle->detail_opt) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return false;
|
|
}
|
|
|
|
if (!insn->id) {
|
|
handle->errnum = CS_ERR_SKIPDATA;
|
|
return false;
|
|
}
|
|
|
|
if (!insn->detail) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return false;
|
|
}
|
|
|
|
return arr_exist8(insn->detail->groups, insn->detail->groups_count, group_id);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
bool CAPSTONE_API cs_reg_read(csh ud, const cs_insn *insn, unsigned int reg_id)
|
|
{
|
|
struct cs_struct *handle;
|
|
if (!ud)
|
|
return false;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle->detail_opt) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return false;
|
|
}
|
|
|
|
if (!insn->id) {
|
|
handle->errnum = CS_ERR_SKIPDATA;
|
|
return false;
|
|
}
|
|
|
|
if (!insn->detail) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return false;
|
|
}
|
|
|
|
return arr_exist(insn->detail->regs_read, insn->detail->regs_read_count, reg_id);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
bool CAPSTONE_API cs_reg_write(csh ud, const cs_insn *insn, unsigned int reg_id)
|
|
{
|
|
struct cs_struct *handle;
|
|
if (!ud)
|
|
return false;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle->detail_opt) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return false;
|
|
}
|
|
|
|
if (!insn->id) {
|
|
handle->errnum = CS_ERR_SKIPDATA;
|
|
return false;
|
|
}
|
|
|
|
if (!insn->detail) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return false;
|
|
}
|
|
|
|
return arr_exist(insn->detail->regs_write, insn->detail->regs_write_count, reg_id);
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
|
|
{
|
|
struct cs_struct *handle;
|
|
unsigned int count = 0, i;
|
|
if (!ud)
|
|
return -1;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle->detail_opt) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return -1;
|
|
}
|
|
|
|
if (!insn->id) {
|
|
handle->errnum = CS_ERR_SKIPDATA;
|
|
return -1;
|
|
}
|
|
|
|
if (!insn->detail) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return -1;
|
|
}
|
|
|
|
handle->errnum = CS_ERR_OK;
|
|
|
|
switch (handle->arch) {
|
|
default:
|
|
handle->errnum = CS_ERR_HANDLE;
|
|
return -1;
|
|
case CS_ARCH_ARM:
|
|
for (i = 0; i < insn->detail->arm.op_count; i++)
|
|
if (insn->detail->arm.operands[i].type == (arm_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_AARCH64:
|
|
for (i = 0; i < insn->detail->aarch64.op_count; i++)
|
|
if (insn->detail->aarch64.operands[i].type == (aarch64_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_X86:
|
|
for (i = 0; i < insn->detail->x86.op_count; i++)
|
|
if (insn->detail->x86.operands[i].type == (x86_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_MIPS:
|
|
for (i = 0; i < insn->detail->mips.op_count; i++)
|
|
if (insn->detail->mips.operands[i].type == (mips_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_PPC:
|
|
for (i = 0; i < insn->detail->ppc.op_count; i++)
|
|
if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_SPARC:
|
|
for (i = 0; i < insn->detail->sparc.op_count; i++)
|
|
if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_SYSZ:
|
|
for (i = 0; i < insn->detail->sysz.op_count; i++)
|
|
if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_XCORE:
|
|
for (i = 0; i < insn->detail->xcore.op_count; i++)
|
|
if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_M68K:
|
|
for (i = 0; i < insn->detail->m68k.op_count; i++)
|
|
if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_TMS320C64X:
|
|
for (i = 0; i < insn->detail->tms320c64x.op_count; i++)
|
|
if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_M680X:
|
|
for (i = 0; i < insn->detail->m680x.op_count; i++)
|
|
if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_EVM:
|
|
break;
|
|
case CS_ARCH_MOS65XX:
|
|
for (i = 0; i < insn->detail->mos65xx.op_count; i++)
|
|
if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_WASM:
|
|
for (i = 0; i < insn->detail->wasm.op_count; i++)
|
|
if (insn->detail->wasm.operands[i].type == (wasm_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_BPF:
|
|
for (i = 0; i < insn->detail->bpf.op_count; i++)
|
|
if (insn->detail->bpf.operands[i].type == (bpf_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_RISCV:
|
|
for (i = 0; i < insn->detail->riscv.op_count; i++)
|
|
if (insn->detail->riscv.operands[i].type == (riscv_op_type)op_type)
|
|
count++;
|
|
break;
|
|
case CS_ARCH_TRICORE:
|
|
for (i = 0; i < insn->detail->tricore.op_count; i++)
|
|
if (insn->detail->tricore.operands[i].type == (tricore_op_type)op_type)
|
|
count++;
|
|
break;
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
|
|
unsigned int post)
|
|
{
|
|
struct cs_struct *handle;
|
|
unsigned int count = 0, i;
|
|
if (!ud)
|
|
return -1;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
if (!handle->detail_opt) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return -1;
|
|
}
|
|
|
|
if (!insn->id) {
|
|
handle->errnum = CS_ERR_SKIPDATA;
|
|
return -1;
|
|
}
|
|
|
|
if (!insn->detail) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return -1;
|
|
}
|
|
|
|
handle->errnum = CS_ERR_OK;
|
|
|
|
switch (handle->arch) {
|
|
default:
|
|
handle->errnum = CS_ERR_HANDLE;
|
|
return -1;
|
|
case CS_ARCH_ARM:
|
|
for (i = 0; i < insn->detail->arm.op_count; i++) {
|
|
if (insn->detail->arm.operands[i].type == (arm_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_AARCH64:
|
|
for (i = 0; i < insn->detail->aarch64.op_count; i++) {
|
|
if (insn->detail->aarch64.operands[i].type == (aarch64_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_X86:
|
|
for (i = 0; i < insn->detail->x86.op_count; i++) {
|
|
if (insn->detail->x86.operands[i].type == (x86_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_MIPS:
|
|
for (i = 0; i < insn->detail->mips.op_count; i++) {
|
|
if (insn->detail->mips.operands[i].type == (mips_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_PPC:
|
|
for (i = 0; i < insn->detail->ppc.op_count; i++) {
|
|
if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_SPARC:
|
|
for (i = 0; i < insn->detail->sparc.op_count; i++) {
|
|
if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_SYSZ:
|
|
for (i = 0; i < insn->detail->sysz.op_count; i++) {
|
|
if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_XCORE:
|
|
for (i = 0; i < insn->detail->xcore.op_count; i++) {
|
|
if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_TRICORE:
|
|
for (i = 0; i < insn->detail->tricore.op_count; i++) {
|
|
if (insn->detail->tricore.operands[i].type == (tricore_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_M68K:
|
|
for (i = 0; i < insn->detail->m68k.op_count; i++) {
|
|
if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_TMS320C64X:
|
|
for (i = 0; i < insn->detail->tms320c64x.op_count; i++) {
|
|
if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_M680X:
|
|
for (i = 0; i < insn->detail->m680x.op_count; i++) {
|
|
if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_EVM:
|
|
#if 0
|
|
for (i = 0; i < insn->detail->evm.op_count; i++) {
|
|
if (insn->detail->evm.operands[i].type == (evm_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
#endif
|
|
break;
|
|
case CS_ARCH_MOS65XX:
|
|
for (i = 0; i < insn->detail->mos65xx.op_count; i++) {
|
|
if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_WASM:
|
|
for (i = 0; i < insn->detail->wasm.op_count; i++) {
|
|
if (insn->detail->wasm.operands[i].type == (wasm_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_BPF:
|
|
for (i = 0; i < insn->detail->bpf.op_count; i++) {
|
|
if (insn->detail->bpf.operands[i].type == (bpf_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_RISCV:
|
|
for (i = 0; i < insn->detail->riscv.op_count; i++) {
|
|
if (insn->detail->riscv.operands[i].type == (riscv_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
case CS_ARCH_SH:
|
|
for (i = 0; i < insn->detail->sh.op_count; i++) {
|
|
if (insn->detail->sh.operands[i].type == (sh_op_type)op_type)
|
|
count++;
|
|
if (count == post)
|
|
return i;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
CAPSTONE_EXPORT
|
|
cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn,
|
|
cs_regs regs_read, uint8_t *regs_read_count,
|
|
cs_regs regs_write, uint8_t *regs_write_count)
|
|
{
|
|
struct cs_struct *handle;
|
|
|
|
if (!ud)
|
|
return -1;
|
|
|
|
handle = (struct cs_struct *)(uintptr_t)ud;
|
|
|
|
#ifdef CAPSTONE_DIET
|
|
// This API does not work in DIET mode
|
|
handle->errnum = CS_ERR_DIET;
|
|
return CS_ERR_DIET;
|
|
#else
|
|
if (!handle->detail_opt) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return CS_ERR_DETAIL;
|
|
}
|
|
|
|
if (!insn->id) {
|
|
handle->errnum = CS_ERR_SKIPDATA;
|
|
return CS_ERR_SKIPDATA;
|
|
}
|
|
|
|
if (!insn->detail) {
|
|
handle->errnum = CS_ERR_DETAIL;
|
|
return CS_ERR_DETAIL;
|
|
}
|
|
|
|
if (handle->reg_access) {
|
|
handle->reg_access(insn, regs_read, regs_read_count, regs_write, regs_write_count);
|
|
} else {
|
|
// this arch is unsupported yet
|
|
handle->errnum = CS_ERR_ARCH;
|
|
return CS_ERR_ARCH;
|
|
}
|
|
|
|
return CS_ERR_OK;
|
|
#endif
|
|
}
|