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21f7bc85f9
* Fix leaks * Remove unnecessary new lines * Add checks for actual buffer length before attempting reading it. * Xtensa: add xtensa support * Xtensa fixes - fix MCExpr - fix Xtensa_add_cs_detail - add `add_cs_detail` - add `MCExpr *MCOperand_getExpr(const MCOperand *MC)` `void printExpr(const MCExpr *E, SStream *O)` autosync fix - fix StreamOperation.py - replace `report_fatal_error` with `CS_ASSERT` - fix patch StreamOperation.py - replace `assert` with `CS_ASSERT` - fix AddCSDetail.py - fix QualifiedIdentifier * Xtensa fix * Xtensa fix .py * add Xtensa to the fuzzer * Xtensa `LITBASE`: add a basic implementation * Xtensa `LITBASE`: add a integration test * Xtensa: fix cs_v6_release_guide.md * Xtensa: fix `XTENSA_OP_GROUP_MEMOPERAND` * Xtensa: fix * Xtensa: fix Targets.py * Use isUint and isInt all over Xtensa * Add documentation about LITBASE functionality * Fix typo * Replace hard with Capstone assert * Xtensa: fix arch_config.json * Xtensa: fix --------- Co-authored-by: Rot127 <unisono@quyllur.org> |
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| .. | ||
| AArch64 | ||
| Alpha | ||
| ARM | ||
| BPF | ||
| HPPA | ||
| LoongArch | ||
| Mips | ||
| PowerPC | ||
| RISCV | ||
| Sparc | ||
| SystemZ | ||
| TriCore | ||
| X86 | ||
| Xtensa | ||
| README.md | ||
Input files for fuzzing input
These files were the legacy test files but replaced.
No it only is consumed by test_corpus3.py to generate input cases for the fuzzer.
Test file formatting
Format of input files:
# ARCH, MODE, OPTION
<hexcode> = <assembly-text>
Example
# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
...