423203 Commits

Author SHA1 Message Date
Simon Pilgrim
72eb630207 [Headers][X86] Enable basic Wdocumentation testing on X86 headers
First part of Issue #35297 - we want to enable Wdocumentation-pedantic as well, but need '\n' support first which Issue #55319 is addressing
2022-05-08 10:53:28 +01:00
Simon Pilgrim
6b3a111a28 [Headers][X86] Replace \operation with \code{.operation}
\operation ... \endoperation are not valid doxygen commands and cause issues when -Wdocumentation is enabled (Issue #35297)

This patch proposes to replace them with \code{.operation} ... \endcode blocks so that the pseudo-code is correctly retained in any documentation and downstream can use the ".operation" type for its own formatting.

Differential Revision: https://reviews.llvm.org/D125170
2022-05-08 10:46:26 +01:00
David Green
6f9e1ea0ef [VectorCombine] Attempt to fold select shuffles from reductions
Given a commutative reduction leading from a shuffle, the order of the
lanes on the shuffle are not important for the result. This means we can
reorder the shuffle to something simpler, which we try shuffling the
first vector lanes first. This was D123494.

The new shuffle may not be profitable though, and if it is not we can
try the folding of select shuffles from D123911. This, with some
adjustment as the output lane ordering is now unimportant, can allow the
final shuffle to simplify given the inputs to the patterns from D123911.
Where as each transformation on their own are not profitable, the
combination is.

We can only support a single shuffle when called from reductions, but we
are able to sort the ReconstructMask, potentially allowing it to
simplify to an identity or concat mask.

Differential Revision: https://reviews.llvm.org/D125086
2022-05-08 10:32:41 +01:00
Simon Pilgrim
f2b1648812 [X86] Fix some signedness errors in x86 headers
Another step toward enabling full -Wsystem-headers testing across all x86 headers

Fix a number of cases where the arg / return value signedness doesn't match the C/C++ intrinsic.

So far I've just added explicit casts as necessary, but we might want to address some of the mismatches directly

Differential Revision: https://reviews.llvm.org/D125164
2022-05-08 09:42:58 +01:00
Vitaly Buka
08ac661248 [test][msan] Relax order of param shadow
Looks like different bots have them in a different order.
2022-05-07 21:17:44 -07:00
Vitaly Buka
009d56da5c [test][msa] Add more sse,avx intrinsics tests 2022-05-07 20:16:22 -07:00
Stella Laurenzo
6dedbcd5e9 Make BinaryStreamWriter::padToAlignment write blocks vs bytes.
While I think this is a performance improvement over the original, this actually fixes a correctness issue: For an appendable underlying stream, padToAlignment would fail if the additional padding would have caused the stream to grow since it was doing its own check on bounds. By deferring to the regular writeArray method this takes the same path as everything else, which does the correct bounds check in WritableBinaryStreamRef::checkOffsetForWrite (i.e. skips the extension check if BSF_Append is set). I had started to fix the existing bounds check in BinaryStreamWriter but deferred to this because it layered better and is more efficient/consistent.

It didn't look like this method was tested at all, so I added a unit test.

Differential Revision: https://reviews.llvm.org/D124746
2022-05-07 17:37:18 -07:00
Sam McCall
6bbf51f3ed [Frontend] Move, don't copy the predefines buffer into PP. NFC.
It's not trivially small, >10kb.
2022-05-08 01:04:46 +02:00
Amaury Séchet
5cd690ad9c Generate sse-intel-ocl.ll automatically. NFC 2022-05-07 22:46:39 +00:00
Amaury Séchet
bead7a2ed5 Regenerate avx512-regcall-NoMask.ll . NFC 2022-05-07 22:27:28 +00:00
Andrew Litteken
e38f014c40 [IROutliner] Accomodate blocks containing PHINodes with one entry outside the region and others inside the region.
When a PHINode has an incoming block from outside the region, it must be handled specially when assigning a global value number to each incoming value. A PHINode has multiple predecessors, and we must handle this case rather than only the single predecessor case.

Reviewer: paquette

Differential Revision: https://reviews.llvm.org/D124777
2022-05-07 17:11:21 -05:00
Simon Pilgrim
a385645b47 [RISCV] Regenerate rv32zbp-zbkb.ll
Noticed in D124839
2022-05-07 21:29:36 +01:00
David Green
830c18047b [AArch64] Add missing NVCAST patterns.
There were apparently some missing NVCAST patterns. This fills them in
using foreach, as opposed to having the specify them individually.

Fixes #55321
2022-05-07 21:08:14 +01:00
Simon Pilgrim
7e3ef7dcd2 [AMDGPU] lowerEXTRACT_VECTOR_ELT - fold from a SCALAR_TO_VECTOR source
As suggested by @foad on D124839

If we're extracting a vector element that originally came from a scalar_to_vector, then avoid the bitcasting of a vector type and perform the shift masking on the (any-extended) scalar source directly, making use of the fact that the upper elements of a scalar_to_vector are all undef.

Differential Revision: https://reviews.llvm.org/D125173
2022-05-07 20:23:31 +01:00
Craig Topper
b81bf7bb2f [LegalizeTypes] Make use of SelectionDAG::getShiftAmountConstant. NFC
Instead of calling getShiftAmountTy and getConstant separately.
2022-05-07 12:16:53 -07:00
Craig Topper
00bfaba997 [LegalizeTypes] Don't assume fshl/fshr shift amount type matches the other operands.
Like other shifts, the type isn't required to match. We shouldn't
assume we can call ZExtPromotedInteger.

I tested the PromoteIntOp_FunnelShift locally by removing the promotion
of the shift amount from PromoteIntRes_FunnelShift. But with the final
version of this patch it is never executed on any tests.

Differential Revision: https://reviews.llvm.org/D125106
2022-05-07 11:44:07 -07:00
Amaury Séchet
06fad8bc05 [DAGCombine] Add node in the worklist in topological order in CombineTo
This is part of an ongoing effort toward making DAGCombine process the nodes in topological order.

This is able to discover a couple of new optimizations, but also causes a couple of regression. I nevertheless chose to submit this patch for review as to start the discussion with people working on the backend so we can find a good way forward.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D124743
2022-05-07 16:24:31 +00:00
Simon Pilgrim
b432f80e48 [ARM] Update ror.ll test to canonicalized IR
As discussed on D124839, we're almost certainly only ever going to see this from IR directly - which now will create funnel shift intrinsics directly

I've also added a couple of rotl(rotr()) tests to check left/right rotation merging.
2022-05-07 17:23:42 +01:00
Simon Pilgrim
e7806c08dc [Headers][X86] amxintrin.h - fixed unknown parameter Wdocumentation warning. NFC
Noticed while triaging Issue #35297
2022-05-07 16:20:39 +01:00
Sam McCall
d44ffd631c [Bitstream] Only consider flushing to file on block boundaries
The goal of flushing to disk is to keep a reasonable bound on peak memory usage.
With a a default threshold of 512MB (and most BitstreamWriters having no backing
file at all), checking after every byte whether to flush seems excessive.

This change makes clangd's unittests run 5% faster (in opt), so it's not
actually free even in the case with no backing file. Likely there are more
important workloads where it makes some difference.

Differential Revision: https://reviews.llvm.org/D125145
2022-05-07 16:57:03 +02:00
Amaury Séchet
c2c259224b const char* for LLVMTargetMachineEmitToFile's argument
The `LLVMTargetMachineEmitToFile` takes a `char* Filename` right now, but it doesn't modify it.
This is annoying to use in the case where you want to pass a const string, because you either have to remove the const, or copy it somewhere else and pass that. Either way, it's not very nice.

I added a const and clang formatted it. This shouldn't break any ABI in my opinion.
I'm sorry but I didn't know whom to put as reviewer for this, so I chose someone with a lot of commits from the .cpp file.

Reviewed By: deadalnix

Differential Revision: https://reviews.llvm.org/D124453
2022-05-07 14:40:55 +00:00
Simon Pilgrim
4750be4907 [X86] Add 32-bit target test coverage to clean header tests 2022-05-07 15:23:46 +01:00
David Green
802e15c576 [SLP] Cluster ordering for loads
Given a load without a better order, this patch partially sorts the
elements to form clusters of adjacent elements in memory. These clusters
can potentially be loaded in fewer loads, meaning less overall shuffling
(for example loading v4i8 clusters of a v16i8 as a single f32 loads, as
opposed to multiple independent bytes loads and inserts).

Differential Revision: https://reviews.llvm.org/D122145
2022-05-07 14:38:11 +01:00
Simon Pilgrim
2cd080c884 [X86] rdrand-builtins.c - add 32-bit target coverage and enable -Wall/-Werror 2022-05-07 14:35:42 +01:00
Amaury Séchet
f4183441d4 Automatically generate aix32-cc-abi-vaarg.ll . NFC 2022-05-07 13:22:40 +00:00
Sanjay Patel
8650f05c97 [InstCombine] fix miscompile when casting int->FP->int
As shown in https://github.com/llvm/llvm-project/issues/55150 -
the existing fold may be wrong when converting to a signed value.
This is a quick fix to avoid the miscompile.

I added tests/comments for all of the signed/unsigned combinations
at either side of the boundary width, and tried to confirm with Alive2:
https://alive2.llvm.org/ce/z/3p9DSu

There are already some TODO items in the test file that suggest
possible refinements, so the regression with ui->FP->si is probably ok.
It seems unlikely that we'd see these kind of edge cases with
non-byte-width integer types in real code. The potential miscompile
went undetected for several years.

This and 747c6a0c734e fixes #55150.

Differential Revision: https://reviews.llvm.org/D124692
2022-05-07 08:46:25 -04:00
Simon Pilgrim
6e345426de [X86] Remove unused 'hint' argument from prefetch tests
hint is a compile time constant and can't be passed in as a variable - we already hardcode
2022-05-07 13:38:40 +01:00
Serge Pavlov
eb28da89a6 [InstCombine] Remove side effect of replaced constrained intrinsics
If a constrained intrinsic call was replaced by some value, it was not
removed in some cases. The dangling instruction resulted in useless
instructions executed in runtime. It happened because constrained
intrinsics usually have side effect, it is used to model the interaction
with floating-point environment. In some cases side effect is actually
absent or can be ignored.

This change adds specific treatment of constrained intrinsics so that
their side effect can be removed if it actually absents.

Differential Revision: https://reviews.llvm.org/D118426
2022-05-07 19:04:11 +07:00
Sam McCall
e571e1a6c3 Reland "[FuzzMutate] Split out FuzzerCLI library that doesn't depend on IR."
This reverts commit a1bb952e833b34fdf03bd571e7f8c948191be018.

I'd somehow missed updating llvm-yaml-parser-fuzzer, now fixed.
2022-05-07 13:49:54 +02:00
Aaron Ballman
a1bb952e83 Revert "[FuzzMutate] Split out FuzzerCLI library that doesn't depend on IR."
This reverts commit 1c5e85b3da649c89db87abecc53b42f6eaa574c2.

It broke a lot of bots with a link error:
https://lab.llvm.org/buildbot/#/builders/171/builds/14222
https://lab.llvm.org/buildbot/#/builders/188/builds/13748
https://lab.llvm.org/buildbot/#/builders/109/builds/38127
2022-05-07 07:29:57 -04:00
Aaron Ballman
8614674b55 Fix underlining in docs to fix the sphinx build 2022-05-07 07:21:43 -04:00
Paul Walker
702c4ade22 [ISD::IndexType] Helper functions for common queries.
Add helper functions to query the signed and scaled properties
of ISD::IndexType along with functions to change them.

Remove setIndexType from MaskedGatherSDNode because it only has
one usage and typically should only be changed alongside its
index operand.

Minimise the direct use of the enum values to lay the groundwork
for more refactoring.

Differential Revision: https://reviews.llvm.org/D123347
2022-05-07 11:23:42 +01:00
Sam McCall
1c5e85b3da [FuzzMutate] Split out FuzzerCLI library that doesn't depend on IR.
All llvm-project fuzzers use this library to parse command-line arguments.
Many of them don't deal with LLVM IR or modules in any way. Bundling those
functions in one library forces build dependencies that don't need to be there.

Among other things, this means check-clang-pseudo no longer depends on most of
LLVM.

Differential Revision: https://reviews.llvm.org/D125081
2022-05-07 12:11:51 +02:00
Sam McCall
0a83ff83af [FuzzMutate] Move LLVM module (de)serialization from FuzzerCLI -> IRMutator. NFC
These are not directly related to the CLI, and are mostly (always?) used when
mutating the modules as part of fuzzing.

Motivation: split FuzzerCLI into its own library that does not depend on IR.
Subprojects that don't use IR should be be fuzzed without the dependency.

Differential Revision: https://reviews.llvm.org/D125080
2022-05-07 12:09:49 +02:00
Simon Pilgrim
eeb44579f1 [X86] Add description comments to SandyBridge for COPY/WriteZero/WriteVecMaskedGatherWriteback cases. NFC.
Match other models.

Use X86WriteRes for WriteVecMaskedGatherWriteback like other models as well.
2022-05-07 10:42:19 +01:00
David Green
2db46db54d [SLP] Add tests for awkward laod orders from SLP. NFC 2022-05-07 10:27:32 +01:00
Chenbing Zheng
394c683d40 [InstCombine] sub(add(X,Y),umin(Y,Z)) --> add(X,usub.sat(Y,Z))
Alive2: https://alive2.llvm.org/ce/z/2UNVbp

Reviewed By: RKSimon, spatel

Differential Revision: https://reviews.llvm.org/D124503
2022-05-07 17:17:48 +08:00
Mehdi Amini
25cd6fba98 Fix MLIR integration test after a8308020 (func. prefix is required bythe parser now) 2022-05-07 09:09:24 +00:00
Chenbing Zheng
1fd7929ae5 [InstCombine] precommit some tests for reassociate add 2022-05-07 15:52:28 +08:00
Chenbing Zheng
8eaa1ef0d8 [InstCombine] add casts from splat-a-bit pattern if necessary
Splatting a bit of constant-index across a value:
sext (ashr (trunc iN X to iM), M-1) to iN --> ashr (shl X, N-M), N-1
If the dest type is different, use a cast (adjust use check).

https://alive2.llvm.org/ce/z/acAan3

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D124590
2022-05-07 15:34:57 +08:00
Petr Hosek
83e07916ff Revert "[CMake][libcxx] Use target_include_directories for libc++ headers"
This reverts commit 203455c85ad03325ce2d77f067f6ac953f2a32ce since
it breaks the OpenMP builders for AMDGPU.
2022-05-06 22:20:06 -07:00
Brad Smith
67b0b02ec9 [libcxx] Remove static inline and make use of _LIBCPP_HIDE_FROM_ABI in __support headers
After feedback from D122861, do the same thing with some of the other headers. Try to move the
headers so they have a similar style and way of doing things.

Reviewed By: ldionne, daltenty

Differential Revision: https://reviews.llvm.org/D124227
2022-05-07 01:14:33 -04:00
Brad Smith
ed85de6db4 [libcxx] random_device, use arc4random() on Solaris
Reviewed By: ldionne

Differential Revision: https://reviews.llvm.org/D125068
2022-05-07 00:59:12 -04:00
Peter S. Housel
1dda6ad80c [test][ORC-RT] Disable elfnix_platform tests on non-x86_64 platforms
ORC ELFNixPlatform currently only supports x86_64.
2022-05-06 20:11:35 -07:00
Petr Hosek
bf3cba71e1 Revert "[runtime] Build compiler-rt with --unwindlib=none"
This reverts commit 102bc634cb4129d9984a8da8515af945e8a5568b because
some tests are failing on sanitizer bots.
2022-05-06 19:53:30 -07:00
Eric Schweitz
1bffc75383 Upstream support for POINTER assignment in FORALL.
Reviewed By: vdonaldson, PeteSteinfeld

Differential Revision: https://reviews.llvm.org/D125140
2022-05-06 19:52:47 -07:00
Petr Hosek
102bc634cb [runtime] Build compiler-rt with --unwindlib=none
This applies the change made to libunwind+libcxxabi+libcxx in D113253
to compiler-rt as well.

Differential Revision: https://reviews.llvm.org/D115674
2022-05-06 17:53:47 -07:00
Petr Hosek
d7732695eb Revert "[runtime] Build compiler-rt with --unwindlib=none"
This reverts commit fecad835fb4c6e65eb487fc626355686959605f6.
2022-05-06 17:52:10 -07:00
Petr Hosek
fecad835fb [runtime] Build compiler-rt with --unwindlib=none
This applies the change made to libunwind+libcxxabi+libcxx in D113253
to compiler-rt as well.

Differential Revision: https://reviews.llvm.org/D115674
2022-05-06 17:36:17 -07:00
Petr Hosek
57636c2590 [CMake] Include llvm-debuginfod-find in Fuchsia toolchain
Differential Revision: https://reviews.llvm.org/D125082
2022-05-06 16:55:05 -07:00