Commit Graph

371836 Commits

Author SHA1 Message Date
Haowei Wu
ad0da312c0 [NFC] Reformat llvm-elfabi
Makes diff in next commit more readable.
2020-11-11 10:41:51 -08:00
Simon Pilgrim
91e3a9c39c [RISCV] srem-vector-lkk.ll - remove unused check prefix 2020-11-11 18:38:23 +00:00
Simon Pilgrim
44882fa104 [Sparc] fp16-promote.ll - Refactor check prefixes + remove unused ones 2020-11-11 18:38:22 +00:00
Simon Pilgrim
5a7be094e3 [SystemZ] Regenerate some fp tests + remove unused check prefixes
Just use default CHECK
2020-11-11 18:38:22 +00:00
Simon Pilgrim
2224c2f8bc [BPF] intrinsic-array-2.ll - remove unused check prefixes
Just use default CHECK
2020-11-11 18:38:21 +00:00
Stella Laurenzo
5fef6ce0cc [mlir][Python] Allow PassManager to interop with the capsule APIs.
* Used in npcomp to cast Python objects via the C-API.

Differential Revision: https://reviews.llvm.org/D91232
2020-11-11 10:37:21 -08:00
Walter Erquinigo
21555fff4d [intel-pt][trace] Implement a "get supported trace type" packet
Depends on D89283.

The goal of this packet (jTraceGetSupportedType) is to be able to query the gdb-server for the tracing technology that can work for the current debuggeer, which can make the user experience simpler but allowing the user to simply type

  thread trace start

to start tracing the current thread without even telling the debugger to use "intel-pt", for example. Similarly, `thread trace start [args...]` would accept args beloging to the working trace type.

Also, if the user typed

  help thread trace start

We could directly show the help information of the trace type that is supported for the target, or mention instead that no tracing is supported, if that's the case.

I added some simple tests, besides, when I ran this on my machine with intel-pt support, I got

  $ process plugin packet send "jTraceSupportedType"
    packet: jTraceSupportedType
  response: {"description":"Intel Processor Trace","pluginName":"intel-pt"}

On a machine without intel-pt support, I got

  $ process plugin packet send "jTraceSupportedType"
    packet: jTraceSupportedType
  response: E00;

Reviewed By: clayborg, labath

Differential Revision: https://reviews.llvm.org/D90490
2020-11-11 10:35:58 -08:00
Fangrui Song
16f8142b11 [llvm-objcopy][ELF] Try fixing non-determinism of Segment::firstSection 2020-11-11 10:20:30 -08:00
Vedant Kumar
d76e01a6a7 [MachO] Allow the LC_IDENT load command
xnu coredumps include an LC_IDENT load command. It's helpful to be able
to just ignore these. IIUC an interested client can grab the identifier
using the MachOObjectFile::load_commands() API.

The status quo is that llvm bails out when it finds an LC_IDENT because
the command is obsolete (see isLoadCommandObsolete).

Differential Revision: https://reviews.llvm.org/D91221
2020-11-11 10:15:54 -08:00
Nikita Popov
782a93cc9a [BasicAA] Add test for incorrect BatchAA result (NFC)
BatchAA produces an incorrect result, because a result based on
a temporary phi noalias assumption is cached.
2020-11-11 19:06:42 +01:00
Simon Pilgrim
deb543ae70 [Driver] hip-toolchain-device-only.hip - remove unused check prefix
Just use default CHECK
2020-11-11 18:00:03 +00:00
Stella Laurenzo
99b1c42fd3 [mlir][Python] Add Windows DLL loader to get python extensions working there.
Differential Revision: https://reviews.llvm.org/D90958
2020-11-11 09:54:47 -08:00
Craig Topper
637f19c36b [RISCV] Remove traces of Glue from RISCVISD::SELECT_CC
We were creating RISCVISD::SELECT_CC nodes with Glue output that was never being used, and the tablegen SDNode had the SDNPInGlue flag instead of the SDNPOutGlue flag.

Since we don't seem to need the Glue just get rid of it from both places.

Differential Revision: https://reviews.llvm.org/D91199
2020-11-11 09:30:48 -08:00
Jessica Paquette
c42053f79b [AArch64][GlobalISel] Select arith extended add/sub in manual selection code
The manual selection code for add/sub was not checking if it was possible to
fold in shifts + extends (the *rx opcode variants).

As a result, we could never select things like

```
cmp x1, w0, uxtw #2
```

Because we don't import any patterns for compares.

This adds support for the arithmetic shifted register forms and updates tests
for instructions selected using `emitADD`, `emitADDS`, and `emitSUBS`.

This is a 0.1% geomean code size improvement on SPECINT2000 at -Os.

Differential Revision: https://reviews.llvm.org/D91207
2020-11-11 09:26:03 -08:00
Fangrui Song
20de182246 [llvm-objcopy] --only-keep-debug: place zero-size segment according to its parent segment
Alternative to D74755. sectionWithinSegment() treats an empty section as having
a size of 1. Due to the rule, an empty .tdata will not be attributed to an
empty PT_TLS. (The empty p_align=64 PT_TLS is for Android Bionic's TCB
compatibility (ELF-TLS). See https://reviews.llvm.org/D62055#1507426)

Currently --only-keep-debug will not layout a segment with no section
(layoutSegmentsForOnlyKeepDebug()), thus p_offset of PT_TLS can go past the end
of the file. The strange p_offset can trigger validation errors for subsequent
tools, e.g. llvm-objcopy errors when reading back the separate debug file
(readProgramHeaders()).

This patch places such an empty segment according to its parent segment.  This
special cases works for the empty PT_TLS used in Android. For a non-empty
segment, it should have at least one non-empty section and will be handled by
the normal code. Note, p_memsz PT_LOAD is rejected by both Linux and FreeBSD.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D90897
2020-11-11 09:21:10 -08:00
Jessica Paquette
f0580c73bb [AArch64][GlobalISel] Select negative arithmetic immediates in manual selector
Previously, we only handled negative arithmetic immediates in the imported
selector code.

Since we don't import code for, say, compares, we were missing opportunities
for things like

```
%cst:gpr(s64) = G_CONSTANT i64 -10
%cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s64), %cst
->
%adds = ADDSXri %reg0, 10, 0, implicit-def $nzcv
%cmp = CSINCWr $wzr, $wzr, 1, implicit $nzcv
```

Instead, we would have to materialize the constant and emit a SUBS.

This adds support for selection like above for SUB, SUBS, ADD, and ADDS.

This is a 0.1% geomean code size improvement on SPECINT2000 at -Os.

Differential Revision: https://reviews.llvm.org/D91108
2020-11-11 09:20:05 -08:00
Jay Foad
f23c4c6f8a [AMDGPU] Separate out real exp instructions by subtarget. NFC.
Differential Revision: https://reviews.llvm.org/D91247
2020-11-11 17:13:40 +00:00
Jay Foad
2b33ea6935 [AMDGPU] Split exp instructions out into their own tablegen file. NFC.
Differential Revision: https://reviews.llvm.org/D91246
2020-11-11 17:13:40 +00:00
Scott Linder
d5f2c3e7c0 [NFC][AMDGPU] Clean up some lit test prefixes
Replace some instances of "ALL" with "GCN" where it applies. Committed
as obvious.
2020-11-11 17:12:37 +00:00
Stella Stamenova
d9624f4448 Revert "[ThreadPlan] Add a test for thread step-in -r, NFC"
This reverts commit ae3640e386.

The new test is failing on the Windows LLDB buildbot.
2020-11-11 09:09:43 -08:00
Jay Foad
f94fd1c8ca [AMDGPU] Make use of SIInstrInfo::isEXP. NFC. 2020-11-11 17:01:20 +00:00
Alex Richardson
fb9942f876 [AsmParser] Add source location to all errors related to .cfi directives
I was trying to add .cfi_ annotations to assembly code in the FreeBSD
kernel and changed a macro that then resulted in incorrectly nested
directives. However, clang's diagnostics said the error was happening at
<unknown>:0. This addresses one of the TODOs added in D51695.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D89787
2020-11-11 17:00:07 +00:00
Alex Lorenz
3df3b62018 [clang] ns_error_domain attribute also supports CFString typed variables
Differential Revision: https://reviews.llvm.org/D90891
2020-11-11 08:50:30 -08:00
Simon Pilgrim
e3b64eb31c [CodeGenCXX] Remove unused check prefixes 2020-11-11 16:19:53 +00:00
Simon Pilgrim
c1e3d38301 [CodeGenOpenCL] Fix check prefix typo on convergent.cl test
Noticed while fixing unused prefix warnings - there isn't actually any diff in the loop unrolled ir between old/new pass managers any more, so the broken checks were superfluous
2020-11-11 15:44:59 +00:00
Simon Pilgrim
10fc39b291 [CodeGenObjC] Remove unused check prefixes 2020-11-11 15:44:58 +00:00
Simon Pilgrim
fc80931b87 [CodeGenCUDA] Fix check prefix typo on device-stub.cu tests
Noticed while fixing unused prefix warnings
2020-11-11 15:44:57 +00:00
Sam McCall
ea4d24c899 [Syntax] Tablegen Sequence classes. NFC
Similar to the previous patch, this doesn't convert *all* the classes that
could be converted. It also doesn't enforce any new invariants etc.

It *does* include some data we don't use yet: specific token types that are
allowed and optional/required status of sequence items. (Similar to Dmitri's
prototype). I think these are easier to add as we go than later, and serve
a useful documentation purpose.

Differential Revision: https://reviews.llvm.org/D90659
2020-11-11 16:29:19 +01:00
Hans Wennborg
418f18c6cd Revert "Reland [CFGuard] Add address-taken IAT tables and delay-load support"
This broke both Firefox and Chromium (PR47905) due to what seems like dllimport
function not being handled correctly.

> This patch adds support for creating Guard Address-Taken IAT Entry Tables (.giats$y sections) in object files, matching the behavior of MSVC. These contain lists of address-taken imported functions, which are used by the linker to create the final GIATS table.
> Additionally, if any DLLs are delay-loaded, the linker must look through the .giats tables and add the respective load thunks of address-taken imports to the GFIDS table, as these are also valid call targets.
>
> Reviewed By: rnk
>
> Differential Revision: https://reviews.llvm.org/D87544

This reverts commit cfd8481da1.
2020-11-11 16:03:33 +01:00
Sam McCall
138189ee33 [Syntax] Tablegen operator<<(NodeKind). NFC
Differential Revision: https://reviews.llvm.org/D90662
2020-11-11 16:02:01 +01:00
Simon Pilgrim
3e5533bafd [CodeGen] Remove unused check prefixes 2020-11-11 14:57:38 +00:00
Simon Pilgrim
8cb97fb9c9 [CodeGen] Fix check prefix mismatch on neon-immediate-ubsan.c tests
Noticed while fixing unused prefix warnings,
2020-11-11 14:57:37 +00:00
Nico Weber
6ab31eeb62 Revert "[hwasan] Fix Thread reuse."
This reverts commit e1eeb026e6.
Test fails: https://reviews.llvm.org/D91208#2388613
2020-11-11 09:56:21 -05:00
Sander de Smalen
30fded75b4 Revert "[LoopVectorizer] NFCI: Calculate register usage based on TLI.getTypeLegalizationCost."
This reverts commits:
* [LoopVectorizer] NFCI: Calculate register usage based on TLI.getTypeLegalizationCost.
  b873aba394.
* [LoopVectorizer] Silence warning in GetRegUsage.
  9ff701100a.
2020-11-11 14:41:55 +00:00
Jay Foad
830ed64ccd Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
This reverts commit 8b08fa0103.

The underlying problems were fixed by D90607.
2020-11-11 14:40:14 +00:00
Simon Pilgrim
f6a326adef [ValueTracking] computeKnownBitsFromShiftOperator - merge zero/one callbacks to single KnownBits callback. NFCI.
Another cleanup for D90479 - handle the Known Ones/Zeros in a single callback, which will make it much easier to jump over to the KnownBits shift handling.
2020-11-11 14:22:42 +00:00
Nico Weber
3109ce51d4 clang-cl: Expose -f[no-]delete-null-pointer-checks as clang-cl flag 2020-11-11 09:19:02 -05:00
Paul Lietar
6fd9e59e1b [mlir] Fix exports in mlir_async_runtime
The MLIR_ASYNCRUNTIME_EXPORT macro was being defined to be either
__declspec(dllexport) or __declspec(dllimport), depending on whether
mlir_c_runner_utils_EXPORTS is defined. The latter was a copy/paste
error and should have been mlir_async_runtime_EXPORTS.

Additionally, the uses of that macro in the .cpp file were unnecessary,
as only function declarations need to be exported, not their definitions.

Differential Revision: https://reviews.llvm.org/D91196
2020-11-11 14:11:16 +00:00
LLVM GN Syncbot
b304025acf [gn build] Port 250de7388b 2020-11-11 14:04:25 +00:00
Elvina Yakubova
624bced7ee [OpenCL] Make Clang recognize -cl-std=1.0 as a value argument
This patch makes Clang recognize -cl-std=1.0 as a value argument,
before only -std=cl1.0 has to be used instead.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47981

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D91237
2020-11-11 17:01:57 +03:00
Adrian Kuegel
a719eef73e MLIR: Remove TanhOp from ops list. It caused a build failure. 2020-11-11 14:58:55 +01:00
Nico Weber
420acc8414 [gn build] (manually) port 98aa067109 2020-11-11 08:40:13 -05:00
Nico Weber
641bead10e [gn build] (semi-manually) Port 454579e46a 2020-11-11 08:40:13 -05:00
Nico Weber
c084ff5819 Revert "[gn build] (semi-manually) Port 98aa067109"
This reverts commit 04ce13e497.
The commit message was wrong. Will reland with fixed message.
2020-11-11 08:40:12 -05:00
Adrian Kuegel
5248047c93 MLIR: add SinOp Lowering to __ocml_sin_f32 and __ocml_sin_f64
This mimics the recent similar patch for GPUToNVVM.

Differential Revision: https://reviews.llvm.org/D91252
2020-11-11 14:38:23 +01:00
Andrzej Warzynski
fdbc7e505c [flang][driver] Make sure that -### is marked as supported (NFC)
`-###` has always been supported in the new flang driver. This patch
merely makes sure that it's included when printing the help screen (i.e.
`flang-new -help`).
2020-11-11 13:12:51 +00:00
Caroline Concatto
37f4ccb275 [AArch64]Add memory op cost model for SVE
This patch adds/fixes memory op cost model for SVE with fixed-width
vector.

Differential Revision: https://reviews.llvm.org/D90950
2020-11-11 12:49:19 +00:00
Nico Weber
04ce13e497 [gn build] (semi-manually) Port 98aa067109 2020-11-11 07:37:15 -05:00
Simon Pilgrim
1a62ca65c1 [KnownBits] Add KnownBits::commonBits helper. NFCI.
We have a frequent pattern where we're merging two KnownBits to get the common/shared bits, and I just fell for the gotcha where I tried to use the & operator to merge them........
2020-11-11 12:15:54 +00:00
Max Kazantsev
c2a7d9f317 [Test] Add failing test for PR48150 2020-11-11 19:11:32 +07:00