452434 Commits

Author SHA1 Message Date
Fangrui Song
d7c459070c [LoopIdiomRecognize] Remove legacy pass
Following recent changes to remove non-core legacy passes.
2023-02-19 21:39:47 -08:00
Alex Brachet
a489e11439 [Fuchsia] Use cleaner method of adding driver binary 2023-02-20 03:57:23 +00:00
Alex Brachet
6bb86689af [Fuchsia] Fix driver build on Windows
Don't include llvm-driver when building for Windows
2023-02-20 03:34:26 +00:00
sstwcw
6e473aeffd [clang-format] Put ports on separate lines in Verilog module headers
New:
```
module mh1
    (input var int in1,
     input var in2, in3,
     output tagged_st out);
endmodule
```

Old:
```
module mh1
    (input var int in1, input var in2, in3, output tagged_st out);
endmodule
```

`getNextNonComment` was modified to return a non-const pointer because
we needed to use it that way in `verilogGroupDecl`.

The comment on line 2626 was a typo.  We corrected it while modifying
the function.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D143825
2023-02-20 03:24:13 +00:00
Chuanqi Xu
55900a0d20 Recommit [Coroutines] Stop supportting std::experimental::coroutine_traits
As we discussed before, we should stop supporting
std::experimental::coroutine_traits in clang17. Now the clang16 is
branched so we can clean them now.

All the removed tests have been duplicated before.
2023-02-20 10:27:02 +08:00
Kai Luo
fd766ba2b1 [GISelEmitter][NFC] Correct path of GISel's td file in the comment.
`include/llvm/CodeGen/TargetGlobalISel.td` no longer exists.
2023-02-20 10:08:01 +08:00
Matt Arsenault
c177051f60 AMDGPU: Restrict foldFreeOpFromSelect combine based on legal source mods
Provides a small code size savings for some f32 cases.
2023-02-19 22:05:54 -04:00
Alex Brachet
55ab77d279 Reland "[Fuchsia] Enable llvm-driver build".
The MacOS problem has been fixed. Additionally, don't enable the
driver build on Windows. We can look into enabling it later if
symlinks work better than I think on Windows.

Differential Revision: https://reviews.llvm.org/D144287
2023-02-20 01:57:40 +00:00
Matt Arsenault
28d8889d27 AMDGPU: Teach fneg combines that select has source modifiers
We do match source modifiers for f32 typed selects already, but the
combiner code was never informed of this.

A long time ago the documentation lied and stated that source
modifiers don't work for v_cndmask_b32 when they in fact do. We had a
bunch fo code operating under the assumption that they don't support
source modifiers, so we tried to move fnegs around to work around
this.

Gets a few small improvements here and there. The main hazard to watch
out for is infinite loops in the combiner since we try to move fnegs
up and down the DAG. For now, don't fold fneg directly into select.
The generic combiner does this for a restricted set of cases
when getNegatedExpression obviously shows an improvement for both
operands. It turns out to be trickier to avoid infinite looping the
combiner in conjunction with pulling out source modifiers, so
leave this for a later commit.
2023-02-19 20:13:38 -04:00
Amara Emerson
66d64aac36 [GlobalISel] Fix a store-merging bug due to use of >= instead of >.
This fixes a corner case where we would skip doing an alias check because of a
>= vs > bug, due to the presence of a non-aliasing instruction, in this case
the load %safeld.

Fixes issue #59376
2023-02-19 15:55:50 -08:00
Alex Brachet
a98cafd1d0 [CMake] Fix driver build on MacOS 2023-02-19 23:42:11 +00:00
Sanjay Patel
8e8467d9d8 [InstCombine] canonicalize "extract lowest set bit" away from cttz intrinsic
1 << (cttz X) --> -X & X
https://alive2.llvm.org/ce/z/qv3E9e

This creates an extra use of the input value, so that's generally
not preferred, but there are advantages to this direction:
1. 'negate' and 'and' allow for better analysis than 'cttz'.
2. This is more likely to induce follow-on transforms (in the
   example from issue #60801, we'll get the decrement pattern).
3. The more basic ALU ops are more likely to result in better
   codegen across a variety of targets.

This won't solve the motivating bugs (see issue #60799) because
we do not recognize the redundant icmp+sel, and the x86 backend
may not have the pattern-matching to produce the optimal BMI
instructions.

Differential Revision: https://reviews.llvm.org/D144329
2023-02-19 17:29:40 -05:00
Erik Desjardins
87d02e0dfd Recommit "[Support] change StringMap hash function from djbHash to xxHash"
This reverts commit 37eb9d13f891f7656f811516e765b929b169afe0.

Test failures have been fixed:

- ubsan failure fixed by 72eac42f21c0f45a27f3eaaff9364cbb5189b9e4
- warn-unsafe-buffer-usage-fixits-local-var-span.cpp fixed by
  03cc52dfd1dbb4a59b479da55e87838fb93d2067 (wasn't related)
- test-output-format.ll failure was spurious, build failed at
  https://lab.llvm.org/buildbot/#/builders/54/builds/3545 (b4431b2d945b6fc19b1a55ac6ce969a8e06e1e93)
  but passed at
  https://lab.llvm.org/buildbot/#/builders/54/builds/3546 (5ae99be0377248c74346096dc475af254a3fc799)
  which is before my revert
  b4431b2d94...5ae99be037

Original commit message:

    Depends on https://reviews.llvm.org/D142861.

    Alternative to https://reviews.llvm.org/D137601.

    xxHash is much faster than djbHash. This makes a simple Rust test case with a large constant string 10% faster to compile.

    Previous attempts at changing this hash function (e.g. https://reviews.llvm.org/D97396) had to be reverted due to breaking tests that depended on iteration order.
    No additional tests fail with this patch compared to `main` when running `check-all` with `-DLLVM_ENABLE_PROJECTS="all"` (on a Linux host), so I hope I found everything that needs to be changed.

    Differential Revision: https://reviews.llvm.org/D142862
2023-02-19 16:52:26 -05:00
Florian Hahn
f61c9b7569
[SLP] Fix infinite loop in isUndefVector.
This fixes an infinite loop if isa<T>(II->getOperand(1)) is true.
Update Base at the top of the loop, before the continue.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D144292
2023-02-19 21:42:24 +00:00
Alex Bradbury
d41a73aa94 [RISCV][MC] Mark Zawrs extension as non-experimental
Support for the unratified 1.0-rc3 specification was introduced in
D133443. The specification has since been ratified (in November 2022
according to the recently ratified extensions list
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>.

A review of the diff
<https://github.com/riscv/riscv-zawrs/compare/V1.0-rc3...main> of the
1.0-rc3 spec vs the current/ratified document shows no changes to the
instruction encoding or naming. At one point, a note was added
<e84f42406a>
indicating Zawrs depends on the Zalrsc extension (not officially
specified, but I believe to be just the LR/SC instructions from the A
extension). The final text ended up as "The instructions in the Zawrs
extension are only useful in conjunction with the LR instructions, which
are provided by the A extension, and which we also expect to be provided
by a narrower Zalrsc extension in the future." I think it's consistent
with this phrasing to not require the A extension for Zawrs, which
matches what was implemented.

No intrinsics are implemented for Zawrs currently, meaning we don't need
to additionally review whether those intrinsics can be considered
finalised and ready for exposure to end users.

Differential Revision: https://reviews.llvm.org/D143507
2023-02-19 20:43:03 +00:00
Craig Topper
7f31a5c4c6 [RISCV] Add fgtq.s and fgeq.s assembler aliases for Zfa.
We can swap operands and use fltq.s and fleq.s. Similar for D and H.
2023-02-19 12:28:01 -08:00
Craig Topper
f962f50fca [RISCV] Remove Commutable property from Zfa fltq/fleq instructions. 2023-02-19 11:37:23 -08:00
Kazu Hirata
cbde2124f1 Use APInt::popcount instead of APInt::countPopulation (NFC)
This is for consistency with the C++20-style bit manipulation
functions in <bit>.
2023-02-19 11:29:12 -08:00
Alex Bradbury
179a24c2f1 [lld][test][RISCV] Don't use incorrectly normalised arch string in riscv-attributes-place.s
Per the psABI, the arch string should be normalised to (amongest other
things) always include the full version of each extension in form
zfoo1p0. riscv-attributes-place.s didn't conform to this, which is not a
problem for the current parsing logic, but this behaviour would change
with a patch I'm about to propose.

This makes riscv-sttributes-place.s feature a valid arch string, and
maintains test coverage for this particular form of invalid arch string
by adding it to riscv-attributes.s.
2023-02-19 19:15:32 +00:00
David Green
fd4d29808e [ARM] Add targets for Arm DebugInfo tests. NFC
This prevents the instructions being invalid for the subtarget.
2023-02-19 19:13:41 +00:00
Florian Hahn
7737c05696
[VPlan] Make sure properlyDominates(A, A) returns false.
At the moment, properlyDominates(A, A) can return true via
LocalComesBefore. Add an early exit to ensure it returns false if
A == B.

Note: no test has been added because the existing test suite covers this
case already with libc++ with assertions enabled.

Fixes https://github.com/llvm/llvm-project/issues/60850.
2023-02-19 18:01:16 +00:00
Mehdi Amini
723cd2e953 Fix potential crash in Flang generateLLVMIR() when MLIR fails to translate to LLVM
This is pure code motion, to ensure that the check if we have a valid llvmModule
comes before trying to set option on this module.

Differential Revision: https://reviews.llvm.org/D144342
2023-02-19 08:55:46 -08:00
Mark de Wever
cf83e79a4b [libc++][format] Disables test on GCC-12.
These tests fail in D144331, for the same reason other format tests fail
in GCC. This is a resource issue.
2023-02-19 16:44:56 +01:00
Carlos Galvez
14fee3d7d3 Fix clang-tools-extra docs build 2023-02-19 13:58:31 +00:00
Carlos Galvez
5b37cddff8 [clang-tidy] Introduce HeaderFileExtensions and ImplementationFileExtensions options
Re-introduce the patch that was reverted previously.
In the first attempt, the checks would not be able to
read from the global option, since getLocalOrGlobal
only works with string types. Additional logic is needed
in order to support both use cases in the transition
period. All that logic will be removed when the local
options are fully removed.

We have a number of checks designed to analyze problems
in header files only, for example:

bugprone-suspicious-include
google-build-namespaces
llvm-header-guard
misc-definitions-in-header
...

All these checks duplicate the same logic and options
to determine whether a location is placed in the main
source file or in the header. More checks are coming
up with similar requirements.

Thus, to remove duplication, let's move this option
to the top-level configuration of clang-tidy (since
it's something all checks should share).

Add a deprecation notice for all checks that use the
local option, prompting to update to the global option.

Differential Revision: https://reviews.llvm.org/D142655
2023-02-19 13:44:11 +00:00
DianQK
1235ed9133
Revert "[SimplifyCFG] Check if the return instruction causes undefined behavior"
This reverts commit b6eed9a82e0ce530d94a194c88615d6c272e1854.
2023-02-19 21:08:29 +08:00
DianQK
b6eed9a82e
[SimplifyCFG] Check if the return instruction causes undefined behavior
This should fix https://github.com/rust-lang/rust/issues/107681.

Return undefined to a noundef return value is undefined.

Example:

```
define noundef i32 @test_ret_noundef(i1 %cond) {
entry:
  br i1 %cond, label %bb1, label %bb2
bb1:
  br label %bb2
bb2:
  %r = phi i32 [ undef, %entry ], [ 1, %bb1 ]
  ret i32 %r
}
```

Differential Revision: https://reviews.llvm.org/D144319
2023-02-19 19:42:40 +08:00
Benjamin Kramer
37f5c598a2 [lldb] Add missing wasm switch case
TypeSystemClang.cpp:4855:13: error: enumeration value 'WasmExternRef' not handled in switch [-Werror,-Wswitch]
2023-02-19 10:54:10 +01:00
Kristina Bessonova
98b9f8620a [BOLT] Attempt to fix bolt/test/runtime/AArch64/adrrelaxationpass.s after D144079
Differential Revision: https://reviews.llvm.org/D144344
2023-02-19 10:10:29 +02:00
Joshua Cao
e19d9eea6e [SCEV] Add automated test checks for some tests 2023-02-18 23:58:23 -08:00
Vitaly Buka
3a3ce59123 [sanitizers] Update global_symbols.txt 2023-02-18 23:40:11 -08:00
NAKAMURA Takumi
c45e90cf15 llvm-tblgen: Anonymize some functions. 2023-02-19 14:44:56 +09:00
Craig Topper
3d0a5bf7de [RISCV] Add Zfa test cases for strict ONE and UEQ comparisons. NFC
These correspond to islessgreater and it inverse.
2023-02-18 17:28:10 -08:00
Fabian
09fd9ef4f4 [mlir] Execute all requested translations in MlirTranslateMain
Currently, MlirTranslateMain only executes one of the requested translations, and does not error if multiple are specified. This commit enables translations to be chained in the specified order.

This makes round-trip tests easier, since existing import/export passes can be reused and no combined round-trip passes have to be registered (example: mlir-translate  -serialize-spirv -deserialize-spirv).

Additionally, by leveraging TranslateRegistration with file-to-file TranslateFunctions, generic pre- and post-processing can be added before/after conversion to/from MLIR.

Reviewed By: lattner, Mogball

Differential Revision: https://reviews.llvm.org/D143719
2023-02-18 21:31:59 +01:00
Craig Topper
78f106a554 [RISCV] Handle RISCVISD::SplitF64 and RISCVISD::BuildPairF64 during isel with Zfa.
Instead of special casing Zfa in the custom inserters, select the
correct instructions during isel.

BuildPairF64 we can do with pattern, but SplitF64 requires custom
selection due to the two destinations.

If we didn't need SplitF64 without Zfa, I would have an extract low
and extract high ISD opcode for Zfa to avoid that issue.
2023-02-18 17:03:55 -08:00
Juneyoung Lee
2ad0cc9186 [DivRemPairs] Strip division's poison generating flag
Given this transformation: X % Y -> X - (X / Y) * Y

This patch strips off the poison-generating flag of X / Y such as exact, because it may make the optimized form result poison whereas X % Y does not.

The issue was reported here: https://github.com/llvm/llvm-project/issues/60748

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D144333
2023-02-18 21:00:55 +00:00
Juneyoung Lee
c726b34ea0 Add a test for D144333 2023-02-18 21:00:55 +00:00
Michael Kirk
c31bc7bdf8 [clang-format] Handle tabs in file path for git-clang-format 2023-02-18 12:56:46 -08:00
Vitaly Buka
a53d940cee [SCEV] Fix FoldID::addInteger(unsigned long I)
"unsigned long" can be 8 bytes, but the code assumes 4.

This this the real root cause D122215 was reverted.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D144316
2023-02-18 12:29:17 -08:00
Vitaly Buka
c23f29d6f0 Revert "[SimplifyCFG] Check if the return instruction causes undefined behavior"
Breaks bots
https://lab.llvm.org/buildbot/#/builders/236/builds/2349
https://lab.llvm.org/buildbot/#/builders/74/builds/17361
https://lab.llvm.org/buildbot/#/builders/168/builds/11972

This reverts commit 7be55b007698f6b6398cbbea69c327b5a971938a.
2023-02-18 12:21:10 -08:00
David Green
8e3dc1366f [AArch64] Concat zip1 and zip2 is a wider zip1
Given concat(zip1(a, b), zip2(a, b)), we can convert that to a 128bit zip1(a, b)
if we widen a and b out first.

Fixes #54226

Differential Revision: https://reviews.llvm.org/D121088
2023-02-18 19:54:29 +00:00
Noah Goldstein
3bd38f6639 [ValueTracking] Add cases for additional ops in isKnownNonZero
Add cases for the following ops:
    - 0-X            -- https://alive2.llvm.org/ce/z/6C75Li
    - bitreverse(X)  -- https://alive2.llvm.org/ce/z/SGG1q9
    - bswap(X)       -- https://alive2.llvm.org/ce/z/p7pzwh
    - ctpop(X)       -- https://alive2.llvm.org/ce/z/c5y3BC
    - abs(X)         -- https://alive2.llvm.org/ce/z/yxXGz_
                        https://alive2.llvm.org/ce/z/rSRg4K
    - uadd_sat(X, Y) -- https://alive2.llvm.org/ce/z/Zw-y4W
                        https://alive2.llvm.org/ce/z/2NRqRz
                        https://alive2.llvm.org/ce/z/M1OpF8

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D142828
2023-02-18 13:45:15 -06:00
Noah Goldstein
e0ce87509b [ValueTracking] Add tests for additional isKnownNonZero cases; NFC
Add cases for the following ops:
    - 0-X
    - bitreverse(X)
    - bswap(X)
    - ctpop(X)
    - abs(X)
    - uadd_sat(X, Y)

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D142827
2023-02-18 13:44:55 -06:00
Noah Goldstein
9a8f517f57 [ValueTracking] Add KnownBits patterns xor(x, x - 1) and and(x, -x) for knowing upper bits to be zero
These two BMI pattern will clear the upper bits of result past the
first set bit. So if we know a single bit in `x` is set, we know that
`results[bitwidth - 1, log2(x) + 1] = 0`.

Alive2:
blsmsk: https://alive2.llvm.org/ce/z/a397BS
blsi: https://alive2.llvm.org/ce/z/tsbQhC

Differential Revision: https://reviews.llvm.org/D142271
2023-02-18 13:31:17 -06:00
Noah Goldstein
c8fb2775ce [ValueTracking] Add tests for known bits after common BMI pattern (blsmsk/blsi); NFC
Differential Revision: https://reviews.llvm.org/D142270
2023-02-18 13:31:12 -06:00
Jay Foad
6749d187c6 [KnownBits] Add blsi and blsmsk
Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D142519
2023-02-18 13:31:07 -06:00
Cyndy Ishida
4384127549
[llvm-tapi-diff] add default case to switch for symbol flags 2023-02-18 11:27:44 -08:00
Cyndy Ishida
b70d87bc5e
[TextAPI] Capture new properties from TBD to InterfaceFile
* Deployment Versions for targets
* Run Search Paths
* Text vs Data Segment attributes to symbols

Reviewed By: pete

Differential Revision: https://reviews.llvm.org/D144158
2023-02-18 10:52:24 -08:00
NAKAMURA Takumi
aeafcbcd75 llvm-tblgen: Add "TableGenBackends.h" to each emitter.
"TableGenBackends.h" has declarations of emitters.
2023-02-19 03:06:32 +09:00
NAKAMURA Takumi
b3405ace95 llvm-tblgen: Add missing includes 2023-02-19 03:06:31 +09:00