1560 Commits

Author SHA1 Message Date
Kristina Bessonova
98b9f8620a [BOLT] Attempt to fix bolt/test/runtime/AArch64/adrrelaxationpass.s after D144079
Differential Revision: https://reviews.llvm.org/D144344
2023-02-19 10:10:29 +02:00
Amir Ayupov
e88122f5f1 [BOLT] Rename BF::isParentFragment -> isChildOf
`isChildOf` is a more concise name for the check. Also, there's no need to
test if the function is a fragment before doing `isChildOf` check.

Reviewed By: #bolt, rafauler, maksfb

Differential Revision: https://reviews.llvm.org/D142667
2023-02-09 10:57:10 -08:00
Amir Ayupov
701109b9b6 [BOLT][Wrapper] Don't compare output upon error exit code
Fix llvm-bolt-wrapper to skip output file checks if llvm-bolt exits with error
code.

Test Plan:
- checkout to revision with invalid NFC mismatch in `is-strip.s` test
  (e.g. 056af487831fb573e6895901d1e48f93922f9635~)
- run `nfc-check-setup.py`
- run `bin/llvm-lit -a tools/bolt/test/X86/is-strip.s`

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D143614
2023-02-09 10:55:12 -08:00
Anton Sidorenko
6820cb2dd5 [Test] Fix YAML mapping keys duplication. NFC.
YAML specification does not allow keys duplication an a mapping. However, YAML
parser in LLVM does not have any check on that and uses only the last key entry.
In this change duplicated keys are merged to satisfy the spec.

Differential Revision: https://reviews.llvm.org/D141848
2023-02-09 12:59:50 +03:00
Amir Ayupov
c49941bd0d [BOLT] Process fragment siblings in lite mode, keep lite mode on
In lite mode, include split function fragments to the list of functions to
process even if a fragment has no samples. This is required to properly
detect and update split jump tables (jump tables that contain pointers to code
in the main and cold fragments).

Reviewed By: #bolt, maksfb

Differential Revision: https://reviews.llvm.org/D140457
2023-02-08 19:11:27 -08:00
yavtuk
0776fc32b1 [BOLT] Search section based on relocation symbol
We need to search referenced section based on relocations symbol section
to properly match end section symbols. For example on some binaries we
can observe that init_array_end/fini_array_end might be "placed" in to
the gap and since no section could be found for address the relocation
would be skipped resulting in wrong ADRP imm after emitting new text
resulting in binary sigsegv.

Credits for the test to Vladislav Khmelevskii aka yota9.
2023-02-08 00:15:56 +03:00
Amir Ayupov
056af48783 [BOLT][TEST] Fix is-strip test for NFC testing 2023-02-07 12:19:00 -08:00
Archibald Elliott
62c7f035b4 [NFC][TargetParser] Remove llvm/ADT/Triple.h
I also ran `git clang-format` to get the headers in the right order for
the new location, which has changed the order of other headers in two
files.
2023-02-07 12:39:46 +00:00
Amir Ayupov
c8482da779 [BOLT] Reintroduce allow-stripped
Reject stripped binaries as a policy.

The core issue with stripped binaries is that we can't detect the presence
of split functions which require extra handling. Therefore BOLT can't ensure
functional correctness of produced binary if the input stripped binary contains
split functions. Supporting such cases is an interesting problem but it goes
against BOLT's intended goal of achieving peak program performance.

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D142686
2023-02-06 18:08:13 -08:00
Amir Ayupov
be2f67c4d8 [BOLT][NFC] Replace anonymous namespace functions with static
Follow LLVM Coding Standards guideline on using anonymous namespaces
(https://llvm.org/docs/CodingStandards.html#anonymous-namespaces)
and use `static` modifier for function definitions.

Reviewed By: #bolt, maksfb

Differential Revision: https://reviews.llvm.org/D143124
2023-02-06 18:05:41 -08:00
Sebastian Pop
9921197920 [AArch64] fix bug #55005 handle DW_CFA_GNU_NegateRAState
GCC on AArch64 uses DW_CFA_GNU_NegateRAState for return address signing.

Differential Revision: https://reviews.llvm.org/D142572
2023-02-04 03:38:19 +00:00
Amir Ayupov
16492a6143 [BOLT][NFC] Rename {MachO,}RewriteInstance::create methods
Follow the code style of fallible constructors in [LLVM Programmer's Manual]
(https://llvm.org/docs/ProgrammersManual.html#fallible-constructors)
and rename `RewriteInstance::createRewriteInstance` to `RewriteInstance::create`

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D143119
2023-02-02 12:30:45 -08:00
Amir Ayupov
726ba82554 [BOLT][NFC] Simplify SW::checkStackPointerRestore
Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D143117
2023-02-02 12:04:17 -08:00
Amir Ayupov
72e5b14fe7 [BOLT][NFC] Use llvm::make_second_range
Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D143019
2023-02-02 12:02:31 -08:00
Amir Ayupov
4177e89354 [BOLT][CMake] Add dependency on llvm_vcsrevision_h
The dependence is needed since Utils includes VCSRevision.h, and other
LLVM components that include this header also have the llvm_vcsrevision_h
dependency.

Fixes #60460.

Reviewed By: #bolt, ayermolo

Differential Revision: https://reviews.llvm.org/D143101
2023-02-01 12:57:50 -08:00
Alexander Yermolovich
864133c5f9 [BOLT][DWARF] Add logging for split dwarf
Added logging when bolt is processing binary with split dwarf.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D142576
2023-01-27 15:50:55 -08:00
Rafael Auler
7768f63e5b [BOLT][NFC] Remove C-style out of bounds array ref
Old code breaks build with libstdc++ with assertions. Fix it.
2023-01-25 12:59:11 -08:00
Amir Ayupov
287508cd9c [BOLT] Use LTO fuzzy name matching in function-order
Allow partial name matching wrt LTO suffixes in `function-order`
user-supplied function list, the same as permitted by profile matching.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D142269
2023-01-25 11:43:10 -08:00
Amir Ayupov
e20074053d [BOLT] Emit a warning about invalid entries in function-order list
Move individual warnings under verbosity >= 1, print out a warning with
aggregate number.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D142397
2023-01-25 11:43:06 -08:00
Jay Foad
fbb003378b [BOLT] Use MCInstrDesc::operands() instead of OpInfo
operands() is the preferred accessor since D142213. OpInfo will be
removed in D142219.

Differential Revision: https://reviews.llvm.org/D142530
2023-01-25 17:26:48 +00:00
Alexander Yermolovich
f230099c13 [BOLT][DWARF] Reuse entries in .debug_addr when not modified
In some binaries produced with ThinLTO there are CUs that share entry in
.debug_addr. Before we would generate a new entry for each. Which lead to binary
size increase. This changes the behavior so that we re-use entries in
.debug_addr.

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D142425
2023-01-24 15:55:03 -08:00
Benjamin Kramer
7557b83aa5 [BOLT] Use range-based implicit def/use accessors. NFCI 2023-01-24 23:12:41 +01:00
Jay Foad
dc4cb724c7 [BOLT] Fix build error after D142214 2023-01-23 13:02:21 +00:00
Amir Ayupov
dbb7316e02 [BOLT][NFC] Move getLTOCommonName to Utils
Reuse getLTOCommonName in components other than Profile (to be used in Core)

Reviewed By: #bolt, maksfb

Differential Revision: https://reviews.llvm.org/D142259
2023-01-20 19:52:14 -08:00
Amir Ayupov
e5e07b01d8 [BOLT] Handle __uniq suffix added by -funique-internal-linkage-names
In profile matching, if `.__uniq` suffix added for internal linkage
symbols with `-funique-internal-linkage-names` prevents BOLT from
matching to a binary function, try to strip the suffix and perform
fuzzy name matching.

Follow-up to D124117.

Reviewed By: #bolt, maksfb

Differential Revision: https://reviews.llvm.org/D142073
2023-01-20 19:23:06 -08:00
Amir Ayupov
86b47f1438 [BOLT][NFC] Move out ReorderFunctions::printStats
Break out stats-printing code from ReorderFunctions::reorder for brevity.

Reviewed By: #bolt, maksfb

Differential Revision: https://reviews.llvm.org/D142250
2023-01-20 15:44:30 -08:00
Alexander Yermolovich
124ca880aa [BOLT][DWARF] Change loclist encoding to use base_addrx
Doing the same thing as for rangelists. Changing loclists to use base_addrx, it
slightly increases .debug_loclists, but reduces .debug_addr section.

| section             | clang-16.bolt.base | clang-16.bolt | raw       |  % |
| debug_loclists |  198208                  |  203398          | 5190     | 102%  |
| .debug_addr    | 14415808              | 14351448        | -64360 |99.5% |

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D141969
2023-01-20 11:30:34 -08:00
Amir Ayupov
69a9bbf106 [BOLT][NFC] Replace ambiguous BinarySection::isReadOnly with isWritable
Address feedback in https://reviews.llvm.org/D102284#2755060

Reviewed By: yota9

Differential Revision: https://reviews.llvm.org/D141733
2023-01-18 14:53:07 -08:00
Amir Ayupov
43f382a9f4 [BOLT][NFC] Simplify handleRelocation
Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D132089
2023-01-18 14:19:35 -08:00
Amir Ayupov
4a7966ea1b [BOLT][NFC] DataAggregator code cleanup
Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D139794
2023-01-18 13:44:44 -08:00
Amir Ayupov
706606a7df [BOLT][NFC] Remove AArch64 override for evaluateBranch
Use MCInstrAnalysis implementation

Reviewed By: #bolt, rafauler, yota9

Differential Revision: https://reviews.llvm.org/D141983
2023-01-18 13:22:57 -08:00
Arthur Eubanks
59bc64c667 [bolt][test] Add REQUIRES: asserts to jt-symbol-disambiguation-3.s
Or else it unexpectedly passes in non-assert builds of bolt.
2023-01-16 17:50:46 -08:00
Joe Loser
a288d7f937 [llvm][ADT] Replace uses of makeMutableArrayRef with deduction guides
Similar to how `makeArrayRef` is deprecated in favor of deduction guides, do the
same for `makeMutableArrayRef`.

Once all of the places in-tree are using the deduction guides for
`MutableArrayRef`, we can mark `makeMutableArrayRef` as deprecated.

Differential Revision: https://reviews.llvm.org/D141814
2023-01-16 14:49:37 -07:00
Maksim Panchenko
27cf96c4ec [BOLT] Minor refactoring for -print-sorted-by option
Only display used values for -print-sorted-by option when printing help.

Differential Revision: https://reviews.llvm.org/D141209
2023-01-12 13:25:36 -08:00
Rafael Auler
e09f6f41ca [BOLT] Add test case triggering JT assertion
Current case that triggers BOLT assertion. Marked XFAIL.
In this test case, we reproduce the behavior seen in gcc where the
base address of a jump table is decremented by some number and ends up
at the exact addess of a jump table from another function. After
linking, the instruction references another jump table and that
confuses BOLT.

Reviewed By: #bolt, Amir

Differential Revision: https://reviews.llvm.org/D138245
2023-01-11 16:50:16 -08:00
Alexander Yermolovich
7fc7934023 [llvm][dwwarf] Change CU/TU index to 64-bit
Changed contribution data structure to 64 bit. I added the 32bit and 64bit
accessors to make it explicit where we use 32bit and where we use 64bit. Also to
make sure sure we catch all the cases where this data structure is used.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D139379
2023-01-11 15:07:11 -08:00
Alexander Yermolovich
6a4a697e17 Revert "[llvm][dwwarf] Change CU/TU index to 64-bit"
This reverts commit fa3fa4d0d42326005dfd5887bf047b86904d3be6.
2023-01-11 14:41:24 -08:00
Denis Revunov
c8ff968b84 [BOLT][AArch64] add lock to FixRelaxations pass
Since the pass is multithreaded, BC.Ctx must be protected. Otherwise we get crashes when processing.

Reviewed by: yota9

Differential Revision: https://reviews.llvm.org/D141465
2023-01-11 05:05:42 -05:00
Alexander Yermolovich
fa3fa4d0d4 [llvm][dwwarf] Change CU/TU index to 64-bit
Changed contribution data structure to 64 bit. I added the 32bit and 64bit
accessors to make it explicit where we use 32bit and where we use 64bit. Also to
make sure sure we catch all the cases where this data structure is used.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D139379
2023-01-10 10:33:52 -08:00
serge-sans-paille
984b800a03
Move from llvm::makeArrayRef to ArrayRef deduction guides - last part
This is a follow-up to https://reviews.llvm.org/D140896, split into
several parts as it touches a lot of files.

Differential Revision: https://reviews.llvm.org/D141298
2023-01-10 11:47:43 +01:00
hezuoqiang
e3b47d31ae [BOLT] Modify the print option to a meaningful value
Using the option `-print-sorted-by=.` cause to core dump, so change to a legal value.

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D140847
2023-01-09 19:05:21 -08:00
Alexander Yermolovich
e22ff52c10 [BOLT][DWARF] Change rangelists to use DW_RLE_offset_pair
Before we always used DW_RLE_startx_length. This is not very efficient and leads
to bigger .debug_addr section. Changed it to use
DW_RLE_base_addressx/DW_RLE_offset_pair.

clang-16 build in debug mode
llvm-bolt ran on it with --update-debug-sections
| section | before | after | diff | % decrease |
| .debug_rnglists | 32732292 | 31986051 | -746241 | 2.3% |
| .debug_addr | 14415808 | 14184128 |  -231680 | 1.6% |

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D140439
2023-01-06 13:45:43 -08:00
Amir Ayupov
be08bb7755 [BOLT][CMake] Add merge-fdata to bolt component
Build and install `merge-fdata` tool as part of `bolt` component:
```
$ ninja bolt
# builds llvm-bolt, perf2bolt and merge-fdata

$ cmake --install . --component bolt --prefix $HOME/test-install-bolt
-- Install configuration: "Release"
-- Install configuration: "Release"
-- Installing: /home/aaupov/test-install-bolt/lib/libbolt_rt_instr.a
-- Installing: /home/aaupov/test-install-bolt/lib/libbolt_rt_hugify.a
-- Installing: /home/aaupov/test-install-bolt/lib/libbolt_rt_instr_osx.a
-- Installing: /home/aaupov/test-install-bolt/bin/llvm-bolt
-- Installing: /home/aaupov/test-install-bolt/bin/perf2bolt
-- Installing: /home/aaupov/test-install-bolt/bin/llvm-boltdiff
-- Installing: /home/aaupov/test-install-bolt/bin/merge-fdata
```

Fixes #57249.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D139972
2023-01-03 17:40:36 -08:00
Amir Ayupov
75c069584a [BOLT][Docs] Add Sphinx documentation
Add stub Sphinx documentation, with configuration copy-pasted from lld and
index page converted from bolt/README.md.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D140156
2023-01-03 17:39:09 -08:00
Amir Ayupov
f40d25dd8d [BOLT][NFC] Use llvm::reverse
Use llvm::reverse instead of `for (auto I = rbegin(), E = rend(); I != E; ++I)`

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D140516
2023-01-03 17:32:11 -08:00
Amir Ayupov
6b05a62a6b [BOLT] Check no-LBR samples in mayHaveProfileData
No-LBR mode wasn't tested and slipped when mayHaveProfileData was added for
Lite mode. This enables processing of profiles collected without LBR and
converted with `perf2bolt -nl` option.

Test Plan:
bin/llvm-lit -a tools/bolt/test/X86/nolbr.s
https://github.com/rafaelauler/bolt-tests/pull/20

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D140256
2023-01-03 14:43:36 -08:00
Kazu Hirata
e8d6c537ac [BOLT] Use std::optional instead of llvm::Optional (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2023-01-02 18:40:21 -08:00
Amir Ayupov
703d94d8f0 [BOLT] Respect -function-order in lite mode
Process functions listed in -function-order file even in lite mode.

Reviewed By: #bolt, maksfb

Differential Revision: https://reviews.llvm.org/D140435
2022-12-28 20:50:20 -08:00
Amir Ayupov
0224bdce92 [BOLT][TEST] Limit iterations in X86/exceptions-pic.test
The test has 3 invocations with 1M iterations each, which adds delay to fast
check-bolt testing. Reduce the number to 1K.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D139651
2022-12-22 19:47:28 -08:00
Vladislav Khmelevsky
17ed8f2928 [BOLT][AArch64] Handle adrp+ld64 linker relaxations
Linker might relax adrp + ldr got address loading to adrp + add for
local non-preemptible symbols (e.g. hidden/protected symbols in
executable). As usually linker doesn't change relocations properly after
relaxation, so we have to handle such cases by ourselves. To do that
during relocations reading we change LD64 reloc to ADD if instruction
mismatch found and introduce FixRelaxationPass that searches for ADRP+ADD
pairs and after performing some checks we're replacing ADRP target symbol
to already fixed ADDs one.

Vladislav Khmelevsky,
Advanced Software Technology Lab, Huawei

Differential Revision: https://reviews.llvm.org/D138097
2022-12-23 01:20:18 +04:00