Commit Graph

75 Commits

Author SHA1 Message Date
xarkes
861648ad49 Renamed sdb models to .sdb.txt () 2017-09-13 09:20:34 +02:00
Fangrui Song
31be3d3ba7 Add instruction descriptions from Intel Instruction Set Reference Volume 2 ()
The descriptions are taken from https://github.com/HJLebbink/x86doc
2017-08-14 11:14:19 +02:00
Fangrui Song
c77aba1c63 PPC: Add all instructions from Power ISA 3.0B () 2017-07-14 10:09:28 +02:00
pancake
bbc508b324 Move lua53 plugins to radare2-extras, available via r2pm
This reverts commit 16c2fd2fe4.
2017-04-05 10:16:50 +02:00
Cararasu
16c2fd2fe4 Lua 5.3 Assembler/Disassembler, Analyzer and Binary Plugin () ()
* Added Lua 5.3 Assembly and Disassembly
* Implemented Lua 5.3 Binary Analyzer 
* removed unnecesasry prints for lua implementation 

* implemented caching for parsing the lua-file  grouped global data together
* added mnemonics to analyzer and fixed a wrong instructionname
* replaced llx and llu with PFMT64x
* removed trailing whitespaces from lua 5.3 assembler and binary analyzer
* made all functions in lua53 plugins that are possible static
2017-04-03 11:59:17 +02:00
pancake
c504b85a7c Fix - Implement s! to show near flag names for history offsets 2017-03-27 13:12:59 +02:00
pancake
6de49610ea Add 40 more asm.describe for Thumb2 2017-03-27 12:38:14 +02:00
pancake
529c578487 Fix rax2 Ox (octal output) 2017-01-09 00:46:32 +01:00
Duncan Ogilvie
e16b490db5 fixed incorrect jna/jbe () 2016-11-12 17:58:00 +01:00
Sebastian Reichel
e9383b1441 Arch independent data in share ()
* magic data is architecture independent

* fcnsign data is architecture independent

* opcode data is architecture independent

* syscall data is architecture independent

* hud data is architecture independent
2016-11-12 11:08:34 +01:00
Duncan Ogilvie
d0cccc5ec7 updated various opcode descriptions () 2016-10-09 19:11:40 +02:00
Duncan Ogilvie
8386438ea0 fixed and added opcode descriptions () 2016-10-07 18:35:40 +02:00
Sylvain Pelissier
bfeff9f10b ARM conditional instruction information () 2016-09-13 15:12:07 +02:00
Karol Harasim
d190e0d3c3 Add description for Xtensa instructions 2016-05-31 21:48:18 +02:00
Duncan Ogilvie
216de66e68 fixed jcc () 2016-05-30 04:21:02 +02:00
Duncan Ogilvie
021a3ea8b2 Update x86 () 2016-05-30 04:20:29 +02:00
Duncan Ogilvie
18ffea18cc added/fixed various cmovXX opcodes ()
As per the Intel manual:

```
CMOVcc - Conditional Move:
| Opcode          | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 47 /r        | CMOVA r16, r/m16  | RM   | Valid      | Valid          | Move if above (CF=0 and ZF=0).         
| REX.W + 0F 43 /r| CMOVAE r64, r/m64 | RM   | Valid      | N.E.           | Move if above or equal (CF=0).         
| 0F 42 /r        | CMOVB r16, r/m16  | RM   | Valid      | Valid          | Move if below (CF=1).                  
| REX.W + 0F 46 /r| CMOVBE r64, r/m64 | RM   | Valid      | N.E.           | Move if below or equal (CF=1 or ZF=1). 
| 0F 42 /r        | CMOVC r16, r/m16  | RM   | Valid      | Valid          | Move if carry (CF=1).                  
| REX.W + 0F 44 /r| CMOVE r64, r/m64  | RM   | Valid      | N.E.           | Move if equal (ZF=1).                  
| 0F 4F /r        | CMOVG r16, r/m16  | RM   | Valid      | Valid          | Move if greater (ZF=0 and SF=OF).      
| REX.W + 0F 4D /r| CMOVGE r64, r/m64 | RM   | Valid      | N.E.           | Move if greater or equal (SF=OF).      
| 0F 4C /r        | CMOVL r16, r/m16  | RM   | Valid      | Valid          | Move if less (SF!= OF).                 
| REX.W + 0F 4E /r| CMOVLE r64, r/m64 | RM   | Valid      | N.E.           | Move if less or equal (ZF=1 or SF!= OF).
| 0F 46 /r        | CMOVNA r16, r/m16 | RM   | Valid      | Valid          | Move if not above (CF=1 or ZF=1).      
| REX.W + 0F 42 /r| CMOVNAE r64, r/m64| RM   | Valid      | N.E.           | Move if not above or equal (CF=1).     
| 0F 43 /r        | CMOVNB r16, r/m16 | RM   | Valid      | Valid          | Move if not below (CF=0).              
| REX.W + 0F 47 /r| CMOVNBE r64, r/m64| RM   | Valid      | N.E.           | Move if not below or equal (CF=0 and   
|                 |                   |      |            |                | ZF=0).                                 
| 0F 43 /r        | CMOVNC r16, r/m16 | RM   | Valid      | Valid          | Move if not carry (CF=0).              
| REX.W + 0F 45 /r| CMOVNE r64, r/m64 | RM   | Valid      | N.E.           | Move if not equal (ZF=0).              
| 0F 4E /r        | CMOVNG r16, r/m16 | RM   | Valid      | Valid          | Move if not greater (ZF=1 or SF!= OF).  
| REX.W + 0F 4C /r| CMOVNGE r64, r/m64| RM   | Valid      | N.E.           | Move if not greater or equal (SF!= OF). 
| 0F 4D /r        | CMOVNL r16, r/m16 | RM   | Valid      | Valid          | Move if not less (SF=OF).              
| REX.W + 0F 4F /r| CMOVNLE r64, r/m64| RM   | Valid      | N.E.           | Move if not less or equal (ZF=0 and    
|                 |                   |      |            |                | SF=OF).                                
| 0F 41 /r        | CMOVNO r16, r/m16 | RM   | Valid      | Valid          | Move if not overflow (OF=0).           
| REX.W + 0F 4B /r| CMOVNP r64, r/m64 | RM   | Valid      | N.E.           | Move if not parity (PF=0).             
| 0F 49 /r        | CMOVNS r16, r/m16 | RM   | Valid      | Valid          | Move if not sign (SF=0).               
| REX.W + 0F 45 /r| CMOVNZ r64, r/m64 | RM   | Valid      | N.E.           | Move if not zero (ZF=0).               
| 0F 40 /r        | CMOVO r16, r/m16  | RM   | Valid      | Valid          | Move if overflow (OF=1).               
| REX.W + 0F 4A /r| CMOVP r64, r/m64  | RM   | Valid      | N.E.           | Move if parity (PF=1).                 
| 0F 4A /r        | CMOVPE r16, r/m16 | RM   | Valid      | Valid          | Move if parity even (PF=1).            
| REX.W + 0F 4B /r| CMOVPO r64, r/m64 | RM   | Valid      | N.E.           | Move if parity odd (PF=0).             
| 0F 48 /r        | CMOVS r16, r/m16  | RM   | Valid      | Valid          | Move if sign (SF=1).                   
| REX.W + 0F 44 /r| CMOVZ r64, r/m64  | RM   | Valid      | N.E.           | Move if zero (ZF=1).
```

* fixed typo

* or -> nor
2016-05-30 04:20:19 +02:00
jvoisin
4b8af71ef4 Removed a duplicate loopne and loopnz entry
removed a duplicate `loopne` and `loopnz` entry
2016-05-25 15:24:13 +02:00
Roman Valls Guimerà
6f66ba9b84 Typo "intro"->"into memory" () 2016-05-24 16:07:38 +02:00
oddcoder
87b6ada97a Add asm.describe for pic18c 2016-03-03 03:18:03 +01:00
mrdanielps
8ee43270e8 V810: Add opcode descriptions 2016-02-11 00:13:27 -06:00
evanrichter
7f43919750 add propeller architecture to asm.describe
source: http://nagasm.org/ASL/Propeller/printedPDF/QuickReference-v15.pdf
2016-02-10 17:21:08 -05:00
Jonathan Neuschäfer
91c940738c Add opcode descriptions for riscv 2016-02-03 11:29:32 +01:00
Jonathan Neuschäfer
edbb677a79 libr/asm/d/arm: Fix description of ORR opcode 2016-02-03 11:22:13 +01:00
condret
f66e7a4c46 fix 2016-02-01 10:09:20 +00:00
Kitsu
73f2995d2e Added tms320 description 2016-01-30 02:50:41 +01:00
Bigendian Smalls
6d1242c18d Added initial documentation for sysz architecture
This will cover 99% of the commands implemented correctly/currently (via
capstone). However, since this doco is a complete list of mnemonics as
of 2016, it will cover all the instructions when a more complete
implementation of sysz is build for r2. Thanks to @mainframed for
parsing the original docs to create the raw instruction files.
2016-01-29 00:02:48 +01:00
Kitsu
a1b872517a Added lm32 description 2016-01-28 23:17:12 +01:00
Kitsu
ea70e2d704 Added missed mnemo in description 2016-01-28 12:22:41 +01:00
Kitsu
990abd338c Added desc to msp430 and fixed mnemo typo rcr -> rrc 2016-01-28 12:22:41 +01:00
Kitsu
6b98a61ae3 Added dalvik description 2016-01-26 21:51:33 +01:00
Maijin
90bc1f37bc Added wpm and extended some descriptions @l4l fix 2016-01-26 15:22:49 +01:00
Kitsu
16c102b2c5 Added i4004 for 2016-01-26 09:38:52 +01:00
Evgeny
0e58051600 Java description fixed
2016-01-25 16:10:17 +01:00
Maijin
28a7dc072f Add i8080/java opcodes, fix x86/sh descriptions thanks @fenugrec @l4l 2016-01-25 12:47:36 +01:00
Maijin
098b7a8d01 Add Malbolge VM opcodes description 2016-01-25 01:08:53 +01:00
Maijin
43d15d5db3 Add SuperH-4 CPU opcodes description thanks @fenugrec 2016-01-25 00:19:58 +01:00
Maijin
29d8456013 Add m68k opcodes descriptions 2016-01-24 13:59:41 +01:00
Maijin
d512751230 Add arc opcodes descriptions 2016-01-23 23:00:34 +01:00
Maijin
273103e66d Add LH5801 opcodes descriptions 2016-01-23 22:43:11 +01:00
Maijin
6f7085e1ba Add description for 8051 opcodes 2016-01-23 22:27:24 +01:00
Maijin
eac6daf88b Add more asm description for MIPS
Add more asm description for MIPS
2016-01-23 21:31:06 +01:00
Maijin
f4c2b98d63 Add some missing description for x86 opcodes 2016-01-09 11:21:50 +01:00
Jeffrey Crowell
d1b5b6ee62 fix doc for x86 enter 2015-12-15 17:56:02 -05:00
Sylvain Pelissier
309e078a8d MIPS instructions information update 2015-11-13 20:48:34 +01:00
Sylvain Pelissier
93f1a17041 MIPS instructions information update 2015-11-10 22:36:22 +01:00
Kiwhacks
eb56f6d424 Add instruction descriptions for SPARC 2015-11-03 22:13:11 +01:00
xambroz
d448260816 build cleanup focused on possibility to control the lib directories with the build parameters
needed mainly for RedHat/Fedora builds
2015-10-27 03:26:45 +01:00
dukeBarman
c381a6cdb8 Add description for AVR instructions with option -w in rasm2 2015-10-01 11:04:36 +02:00
Ricardo Quesada
6966b2b6f3 adds 6502 opcode description
to be used with `?d`
eg:
`?d cli`
2015-09-18 17:17:24 +02:00