* add init support for IRG ins, fails tests
* update irg instruction correctness, might still be issue with sp test case
* add third test example for irg based on binja
* remove unness masking, fix xzr value in irg
* add init support for addg, fails tests
* refactor irg encoding
* fix test formatting
* add addg instruction - passes test
* enable assembler tests for more mte instructions
* cleanup some error checking, add skele for detecting stg ins
* add init support for subg
* Add support for GMI instruction
* Add more tests for different kinds of store tag addr modes
* Add a few more instructions (subp, stg)
STG passes for pre-index and signed immediate tests, but still has an issue with post-indexing
* Add ldg instruction
* Add CMPP / SUBPS instruction that passes test
* Activate tests for more mte instructions
Currently disable subp as the encoding appears to be off and requires further investigation
* Add LDGM instruction
* anal.cc tests are the only tests marked as broken
* Bonus points: minor code cleanup here and there
* Thanks to Luc for all the work and chats to make it happen
Current code unconditionally drops last 2 bits without checking if those 2 bits are set or cleared,
if ignored these 2 bits are eventually lost and not encoded in machine instruction
and it's dangerous to assume destination supplied is valid to correct this I implemented a check.
Last 2 bits are discarded when final machine instruction is generated
and later in the decode phase this 14 bit immediate value (destination) is shifted left 2 bit positions,
and later sign extended to 64 bits that means we can actually encode a number with 16 bits but current code encodes only upto 14 bits. Thus, wasting 2 bits.
Also, Current code unconditionally parses last 5 bits from immediate 1, which is nothing but bit number to be tested in the register. Therefore, it must be within range 0-31 if 32 bit register is used, range must 0-63 if 64 bit register is used.
Also, in the case of 64 bit register only last 5 bits are encoded because it's later concatenated with MSB hence rendering a 6 bit number that can be used to denote bit positions between 0-63. To tackle this a check for this is implemented.
At last testcases are added to demonstrate these checks.
* Fix asm.acur supporting arch, anal and asm plugins ##arch
* Fixes the arch/bits combo selection order issue for riscv tests
* Move the riscv arch plugin to the new plugin structure
* Deprecate r_asm_setup ()
