mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 12:50:30 +00:00
TargetInstrInfo hooks implemented in codegen should be declared pure virtual.
llvm-svn: 158233
This commit is contained in:
parent
03f9c316e2
commit
151209d9dc
@ -650,7 +650,7 @@ public:
|
|||||||
/// getNumMicroOps - Return the number of u-operations the given machine
|
/// getNumMicroOps - Return the number of u-operations the given machine
|
||||||
/// instruction will be decoded to on the target cpu.
|
/// instruction will be decoded to on the target cpu.
|
||||||
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
|
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *MI) const;
|
const MachineInstr *MI) const = 0;
|
||||||
|
|
||||||
/// isZeroCost - Return true for pseudo instructions that don't consume any
|
/// isZeroCost - Return true for pseudo instructions that don't consume any
|
||||||
/// machine resources in their current form. These are common cases that the
|
/// machine resources in their current form. These are common cases that the
|
||||||
@ -675,7 +675,7 @@ public:
|
|||||||
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *DefMI, unsigned DefIdx,
|
const MachineInstr *DefMI, unsigned DefIdx,
|
||||||
const MachineInstr *UseMI,
|
const MachineInstr *UseMI,
|
||||||
unsigned UseIdx) const;
|
unsigned UseIdx) const = 0;
|
||||||
|
|
||||||
/// computeOperandLatency - Compute and return the latency of the given data
|
/// computeOperandLatency - Compute and return the latency of the given data
|
||||||
/// dependent def and use when the operand indices are already known.
|
/// dependent def and use when the operand indices are already known.
|
||||||
@ -714,7 +714,7 @@ public:
|
|||||||
/// PredCost.
|
/// PredCost.
|
||||||
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *MI,
|
const MachineInstr *MI,
|
||||||
unsigned *PredCost = 0) const;
|
unsigned *PredCost = 0) const = 0;
|
||||||
|
|
||||||
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
||||||
SDNode *Node) const = 0;
|
SDNode *Node) const = 0;
|
||||||
@ -744,7 +744,7 @@ public:
|
|||||||
/// if the target considered it 'low'.
|
/// if the target considered it 'low'.
|
||||||
virtual
|
virtual
|
||||||
bool hasLowDefLatency(const InstrItineraryData *ItinData,
|
bool hasLowDefLatency(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *DefMI, unsigned DefIdx) const;
|
const MachineInstr *DefMI, unsigned DefIdx) const = 0;
|
||||||
|
|
||||||
/// verifyInstruction - Perform target specific instruction verification.
|
/// verifyInstruction - Perform target specific instruction verification.
|
||||||
virtual
|
virtual
|
||||||
@ -901,14 +901,34 @@ public:
|
|||||||
virtual bool isSchedulingBoundary(const MachineInstr *MI,
|
virtual bool isSchedulingBoundary(const MachineInstr *MI,
|
||||||
const MachineBasicBlock *MBB,
|
const MachineBasicBlock *MBB,
|
||||||
const MachineFunction &MF) const;
|
const MachineFunction &MF) const;
|
||||||
using TargetInstrInfo::getOperandLatency;
|
|
||||||
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
||||||
SDNode *DefNode, unsigned DefIdx,
|
SDNode *DefNode, unsigned DefIdx,
|
||||||
SDNode *UseNode, unsigned UseIdx) const;
|
SDNode *UseNode, unsigned UseIdx) const;
|
||||||
using TargetInstrInfo::getInstrLatency;
|
|
||||||
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
||||||
SDNode *Node) const;
|
SDNode *Node) const;
|
||||||
|
|
||||||
|
using TargetInstrInfo::getNumMicroOps;
|
||||||
|
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
|
||||||
|
const MachineInstr *MI) const;
|
||||||
|
|
||||||
|
using TargetInstrInfo::getInstrLatency;
|
||||||
|
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
|
||||||
|
const MachineInstr *MI,
|
||||||
|
unsigned *PredCost = 0) const;
|
||||||
|
|
||||||
|
using TargetInstrInfo::hasLowDefLatency;
|
||||||
|
virtual
|
||||||
|
bool hasLowDefLatency(const InstrItineraryData *ItinData,
|
||||||
|
const MachineInstr *DefMI, unsigned DefIdx) const;
|
||||||
|
|
||||||
|
using TargetInstrInfo::getOperandLatency;
|
||||||
|
virtual int getOperandLatency(const InstrItineraryData *ItinData,
|
||||||
|
const MachineInstr *DefMI, unsigned DefIdx,
|
||||||
|
const MachineInstr *UseMI,
|
||||||
|
unsigned UseIdx) const;
|
||||||
|
|
||||||
bool usePreRAHazardRecognizer() const;
|
bool usePreRAHazardRecognizer() const;
|
||||||
|
|
||||||
virtual ScheduleHazardRecognizer *
|
virtual ScheduleHazardRecognizer *
|
||||||
|
@ -554,8 +554,8 @@ int TargetInstrInfoImpl::getInstrLatency(const InstrItineraryData *ItinData,
|
|||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
unsigned
|
unsigned
|
||||||
TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
|
TargetInstrInfoImpl::getNumMicroOps(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *MI) const {
|
const MachineInstr *MI) const {
|
||||||
if (!ItinData || ItinData->isEmpty())
|
if (!ItinData || ItinData->isEmpty())
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
@ -579,9 +579,10 @@ unsigned TargetInstrInfo::defaultDefLatency(const InstrItineraryData *ItinData,
|
|||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
unsigned TargetInstrInfoImpl::
|
||||||
const MachineInstr *MI,
|
getInstrLatency(const InstrItineraryData *ItinData,
|
||||||
unsigned *PredCost) const {
|
const MachineInstr *MI,
|
||||||
|
unsigned *PredCost) const {
|
||||||
// Default to one cycle for no itinerary. However, an "empty" itinerary may
|
// Default to one cycle for no itinerary. However, an "empty" itinerary may
|
||||||
// still have a MinLatency property, which getStageLatency checks.
|
// still have a MinLatency property, which getStageLatency checks.
|
||||||
if (!ItinData)
|
if (!ItinData)
|
||||||
@ -590,9 +591,9 @@ unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
|||||||
return ItinData->getStageLatency(MI->getDesc().getSchedClass());
|
return ItinData->getStageLatency(MI->getDesc().getSchedClass());
|
||||||
}
|
}
|
||||||
|
|
||||||
bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
|
bool TargetInstrInfoImpl::hasLowDefLatency(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *DefMI,
|
const MachineInstr *DefMI,
|
||||||
unsigned DefIdx) const {
|
unsigned DefIdx) const {
|
||||||
if (!ItinData || ItinData->isEmpty())
|
if (!ItinData || ItinData->isEmpty())
|
||||||
return false;
|
return false;
|
||||||
|
|
||||||
@ -603,11 +604,10 @@ bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
|
|||||||
|
|
||||||
/// Both DefMI and UseMI must be valid. By default, call directly to the
|
/// Both DefMI and UseMI must be valid. By default, call directly to the
|
||||||
/// itinerary. This may be overriden by the target.
|
/// itinerary. This may be overriden by the target.
|
||||||
int
|
int TargetInstrInfoImpl::
|
||||||
TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
|
getOperandLatency(const InstrItineraryData *ItinData,
|
||||||
const MachineInstr *DefMI, unsigned DefIdx,
|
const MachineInstr *DefMI, unsigned DefIdx,
|
||||||
const MachineInstr *UseMI,
|
const MachineInstr *UseMI, unsigned UseIdx) const {
|
||||||
unsigned UseIdx) const {
|
|
||||||
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
||||||
unsigned UseClass = UseMI->getDesc().getSchedClass();
|
unsigned UseClass = UseMI->getDesc().getSchedClass();
|
||||||
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
||||||
|
Loading…
Reference in New Issue
Block a user