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[x86] Accept 'retn' as an alias to 'ret[lqw]'\'ret' (At&t\Intel)

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Implement 'retn' simply by aliasing it to the relevant 'ret' instruction

Commit on behalf of coby

Differential Revision: https://reviews.llvm.org/D24346

llvm-svn: 282601
This commit is contained in:
Marina Yatsina 2016-09-28 15:52:56 +00:00
parent 080cb64e9c
commit 269811ad82
2 changed files with 22 additions and 0 deletions
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6
lib/Target/X86/X86InstrInfo.td
View File

@ -2630,6 +2630,12 @@ def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
// Apply 'ret' behavior to 'retn'
def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>;
def : MnemonicAlias<"retn", "ret", "intel">;
def : MnemonicAlias<"sal", "shl", "intel">;
def : MnemonicAlias<"salb", "shlb", "att">;
def : MnemonicAlias<"salw", "shlw", "att">;

16
test/MC/X86/ret.s
View File

@ -57,6 +57,22 @@
// ERR32: error: instruction requires: 64-bit mode
// ERR16: error: instruction requires: 64-bit mode
retn
// 64: retq
// 64: encoding: [0xc3]
// 32: retl
// 32: encoding: [0xc3]
// 16: retw
// 16: encoding: [0xc3]
retn $0
// 64: retq $0
// 64: encoding: [0xc2,0x00,0x00]
// 32: retl $0
// 32: encoding: [0xc2,0x00,0x00]
// 16: retw $0
// 16: encoding: [0xc2,0x00,0x00]
lret
// 64: lretl
// 64: encoding: [0xcb]