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AMDGPU: Change control flow intrinsics to use amdgcn prefix
These aren't supposed to be used outside of the backend, so there aren't any users to worry about. llvm-svn: 258516
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@ -34,13 +34,13 @@ typedef std::pair<BasicBlock *, Value *> StackEntry;
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typedef SmallVector<StackEntry, 16> StackVector;
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// Intrinsic names the control flow is annotated with
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static const char *const IfIntrinsic = "llvm.SI.if";
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static const char *const ElseIntrinsic = "llvm.SI.else";
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static const char *const BreakIntrinsic = "llvm.SI.break";
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static const char *const IfBreakIntrinsic = "llvm.SI.if.break";
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static const char *const ElseBreakIntrinsic = "llvm.SI.else.break";
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static const char *const LoopIntrinsic = "llvm.SI.loop";
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static const char *const EndCfIntrinsic = "llvm.SI.end.cf";
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static const char *const IfIntrinsic = "llvm.amdgcn.if";
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static const char *const ElseIntrinsic = "llvm.amdgcn.else";
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static const char *const BreakIntrinsic = "llvm.amdgcn.break";
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static const char *const IfBreakIntrinsic = "llvm.amdgcn.if.break";
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static const char *const ElseBreakIntrinsic = "llvm.amdgcn.else.break";
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static const char *const LoopIntrinsic = "llvm.amdgcn.loop";
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static const char *const EndCfIntrinsic = "llvm.amdgcn.end.cf";
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class SIAnnotateControlFlow : public FunctionPass {
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@ -1874,14 +1874,14 @@ def SI_IF: InstSI <
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(outs SReg_64:$dst),
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(ins SReg_64:$vcc, brtarget:$target),
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"",
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[(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
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[(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))]
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>;
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def SI_ELSE : InstSI <
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(outs SReg_64:$dst),
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(ins SReg_64:$src, brtarget:$target),
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"",
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[(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
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[(set i64:$dst, (int_amdgcn_else i64:$src, bb:$target))]
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> {
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let Constraints = "$src = $dst";
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}
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@ -1890,7 +1890,7 @@ def SI_LOOP : InstSI <
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(outs),
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(ins SReg_64:$saved, brtarget:$target),
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"si_loop $saved, $target",
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[(int_SI_loop i64:$saved, bb:$target)]
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[(int_amdgcn_loop i64:$saved, bb:$target)]
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>;
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} // end isBranch = 1, isTerminator = 1
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@ -1899,28 +1899,28 @@ def SI_BREAK : InstSI <
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(outs SReg_64:$dst),
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(ins SReg_64:$src),
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"si_else $dst, $src",
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[(set i64:$dst, (int_SI_break i64:$src))]
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[(set i64:$dst, (int_amdgcn_break i64:$src))]
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>;
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def SI_IF_BREAK : InstSI <
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(outs SReg_64:$dst),
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(ins SReg_64:$vcc, SReg_64:$src),
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"si_if_break $dst, $vcc, $src",
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[(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
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[(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]
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>;
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def SI_ELSE_BREAK : InstSI <
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(outs SReg_64:$dst),
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(ins SReg_64:$src0, SReg_64:$src1),
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"si_else_break $dst, $src0, $src1",
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[(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
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[(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))]
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>;
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def SI_END_CF : InstSI <
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(outs),
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(ins SReg_64:$saved),
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"si_end_cf $saved",
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[(int_SI_end_cf i64:$saved)]
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[(int_amdgcn_end_cf i64:$saved)]
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>;
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} // End Uses = [EXEC], Defs = [EXEC]
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@ -186,14 +186,16 @@ let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
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} // End TargetPrefix = "SI", isTarget = 1
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let TargetPrefix = "amdgcn", isTarget = 1 in {
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/* Control flow Intrinsics */
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def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
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def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
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def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
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def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
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def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
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def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
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def int_amdgcn_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_amdgcn_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
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def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
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def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
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def int_amdgcn_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_amdgcn_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
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}
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