RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-26 14:16:12 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Expand pseudo/macro BteqzT8SltuX16 . There is no test case because

Browse Source 
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.

llvm-svn: 175419
This commit is contained in:
Reed Kotler 2013-02-18 04:55:38 +00:00
parent 8e9b3f2984
commit 8b4a359a59
2 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -142,6 +142,11 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
case Mips::BteqzT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
break;
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;

2
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -1012,6 +1012,8 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
// Purpose: Set on Less Than Unsigned
// To record the result of an unsigned less-than comparison.
//
def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>;
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
let isCodeGenOnly=1;
}