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[X86] Use getRegClassFor to simplify some code in fast isel. NFCI
No need to select the register class based on type and features. It should already be setup by X86ISelLowering. llvm-svn: 360513
This commit is contained in:
Craig Topper
parent
16055b8837
commit
9c17901350
@ -84,7 +84,7 @@ private:
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bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT,
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const DebugLoc &DL);
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bool X86FastEmitLoad(EVT VT, X86AddressMode &AM, MachineMemOperand *MMO,
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bool X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO,
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unsigned &ResultReg, unsigned Alignment = 1);
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bool X86FastEmitStore(EVT VT, const Value *Val, X86AddressMode &AM,
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@ -314,7 +314,7 @@ bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
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/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
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/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
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/// Return true and the result register by reference if it is possible.
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bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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bool X86FastISel::X86FastEmitLoad(MVT VT, X86AddressMode &AM,
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MachineMemOperand *MMO, unsigned &ResultReg,
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unsigned Alignment) {
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bool HasSSE41 = Subtarget->hasSSE41();
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@ -324,46 +324,38 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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bool HasVLX = Subtarget->hasVLX();
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bool IsNonTemporal = MMO && MMO->isNonTemporal();
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// Treat i1 loads the same as i8 loads. Masking will be done when storing.
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if (VT == MVT::i1)
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VT = MVT::i8;
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = nullptr;
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switch (VT.getSimpleVT().SimpleTy) {
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switch (VT.SimpleTy) {
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default: return false;
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case MVT::i1:
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = &X86::GR8RegClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = &X86::GR16RegClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = &X86::GR32RegClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = &X86::GR64RegClass;
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break;
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case MVT::f32:
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if (X86ScalarSSEf32) {
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if (X86ScalarSSEf32)
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Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
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RC = HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass;
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} else {
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else
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Opc = X86::LD_Fp32m;
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RC = &X86::RFP32RegClass;
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}
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break;
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case MVT::f64:
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if (X86ScalarSSEf64) {
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if (X86ScalarSSEf64)
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Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm;
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RC = HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass;
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} else {
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else
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Opc = X86::LD_Fp64m;
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RC = &X86::RFP64RegClass;
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}
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break;
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case MVT::f80:
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// No f80 support yet.
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@ -378,7 +370,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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else
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Opc = HasVLX ? X86::VMOVUPSZ128rm :
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HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm;
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RC = HasVLX ? &X86::VR128XRegClass : &X86::VR128RegClass;
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break;
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case MVT::v2f64:
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if (IsNonTemporal && Alignment >= 16 && HasSSE41)
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@ -390,7 +381,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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else
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Opc = HasVLX ? X86::VMOVUPDZ128rm :
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HasAVX ? X86::VMOVUPDrm : X86::MOVUPDrm;
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RC = HasVLX ? &X86::VR128XRegClass : &X86::VR128RegClass;
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break;
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case MVT::v4i32:
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case MVT::v2i64:
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@ -405,7 +395,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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else
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Opc = HasVLX ? X86::VMOVDQU64Z128rm :
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HasAVX ? X86::VMOVDQUrm : X86::MOVDQUrm;
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RC = HasVLX ? &X86::VR128XRegClass : &X86::VR128RegClass;
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break;
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case MVT::v8f32:
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assert(HasAVX);
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@ -417,7 +406,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm;
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else
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Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm;
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RC = HasVLX ? &X86::VR256XRegClass : &X86::VR256RegClass;
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break;
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case MVT::v4f64:
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assert(HasAVX);
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@ -429,7 +417,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm;
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else
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Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm;
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RC = HasVLX ? &X86::VR256XRegClass : &X86::VR256RegClass;
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break;
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case MVT::v8i32:
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case MVT::v4i64:
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@ -444,7 +431,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm;
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else
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Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm;
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RC = HasVLX ? &X86::VR256XRegClass : &X86::VR256RegClass;
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break;
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case MVT::v16f32:
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assert(HasAVX512);
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@ -452,7 +438,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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Opc = X86::VMOVNTDQAZrm;
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else
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Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm;
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RC = &X86::VR512RegClass;
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break;
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case MVT::v8f64:
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assert(HasAVX512);
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@ -460,7 +445,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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Opc = X86::VMOVNTDQAZrm;
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else
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Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm;
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RC = &X86::VR512RegClass;
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break;
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case MVT::v8i64:
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case MVT::v16i32:
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@ -473,10 +457,11 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
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Opc = X86::VMOVNTDQAZrm;
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else
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Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm;
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RC = &X86::VR512RegClass;
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break;
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}
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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ResultReg = createResultReg(RC);
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MachineInstrBuilder MIB =
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
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@ -3754,26 +3739,19 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
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unsigned Opc = 0;
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bool HasAVX = Subtarget->hasAVX();
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bool HasAVX512 = Subtarget->hasAVX512();
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const TargetRegisterClass *RC = nullptr;
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switch (VT.SimpleTy) {
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default: return 0;
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case MVT::f32:
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if (X86ScalarSSEf32) {
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if (X86ScalarSSEf32)
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Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
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RC = HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass;
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} else {
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else
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Opc = X86::LD_Fp32m;
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RC = &X86::RFP32RegClass;
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}
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break;
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case MVT::f64:
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if (X86ScalarSSEf64) {
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if (X86ScalarSSEf64)
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Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm;
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RC = HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass;
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} else {
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else
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Opc = X86::LD_Fp64m;
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RC = &X86::RFP64RegClass;
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}
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break;
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case MVT::f80:
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// No f80 support yet.
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@ -3799,7 +3777,7 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
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// Create the load from the constant pool.
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unsigned CPI = MCP.getConstantPoolIndex(CFP, Align);
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unsigned ResultReg = createResultReg(RC);
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
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if (CM == CodeModel::Large) {
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unsigned AddrReg = createResultReg(&X86::GR64RegClass);
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