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Subtract instructions; minor cleanups

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llvm-svn: 12111
This commit is contained in:
Brian Gaeke 2004-03-04 04:37:45 +00:00
parent 0d71671bcf
commit b2f869ee43
2 changed files with 10 additions and 5 deletions
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10
lib/Target/SparcV8/InstSelectSimple.cpp
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@ -165,9 +165,8 @@ static TypeClass getClass (const Type *T) {
void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Constant *C, unsigned R) {
if (C->getType()->isIntegral()) {
if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
unsigned Class = getClass(C->getType());
ConstantInt *CI = cast<ConstantInt>(C);
switch (Class) {
case cByte:
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
@ -185,12 +184,12 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
return;
}
default:
assert (0 && "Can't move this kind of constant");
assert (0 && "Can't copy this kind of constant into register yet");
return;
}
}
assert (0 && "Can't copy constants into registers yet");
assert (0 && "Can't copy this kind of constant into register yet");
}
bool V8ISel::runOnFunction(Function &Fn) {
@ -246,6 +245,9 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Sub:
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
default:
visitInstruction (I);
return;

5
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -62,7 +62,7 @@ def CALL : InstV8 {
let Name = "call";
}
// Section B.9 - SETHI Instruction, p. 102
// Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100, "sethi">;
// Section B.11 - Logical Instructions, p. 106
@ -78,6 +78,9 @@ def SRAri : F3_1<2, 0b100111, "sra">;
// Section B.13 - Add Instructions, p. 108
def ADDrr : F3_1<2, 0b000000, "add">;
// Section B.15 - Subtract Instructions, p. 110
def SUBrr : F3_1<2, 0b000100, "sub">;
// Section B.25 - Jump and Link, p. 126
def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd