Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.
llvm-svn: 6619
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
llvm-svn: 6564
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
llvm-svn: 6548
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
llvm-svn: 6384
