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4518 Commits

Author SHA1 Message Date
Mon P Wang
08d3b69861 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
llvm-svn: 131085
 2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen
4a57c64408 Eliminate the ARM sub-register indexes that are not needed by the sources. 
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.

llvm-svn: 131059
 2011-05-07 21:22:42 +00:00
Eric Christopher
47f9c0695c Fix the non-MC encoding of pkhbt and pkhtb. 
Patch by Stephen Hines.

llvm-svn: 131045
 2011-05-07 04:37:27 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Rafael Espindola
59462d8ae3 Dead code elimination. 
llvm-svn: 130984
 2011-05-06 14:56:22 +00:00
Devang Patel
8823e24dde Do not emit location expression size twice. 
llvm-svn: 130854
 2011-05-04 19:00:57 +00:00
Jakob Stoklund Olesen
da28d31f03 Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. 
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

llvm-svn: 130801
 2011-05-03 22:31:24 +00:00
Bob Wilson
7ca16f2c1f Temporarily disable use of divmod compiler-rt functions for iOS. 
llvm-svn: 130766
 2011-05-03 17:33:22 +00:00
Bruno Cardoso Lopes
c818d784a2 Fold ARM coprocessor intrinsics patterns into the instructions defs whenever 
it's possible.

llvm-svn: 130764
 2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
9dd575e4a9 Add a few ARM coprocessor intrinsics. Testcases included 
llvm-svn: 130763
 2011-05-03 17:29:22 +00:00
Dan Gohman
7beb845bab Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.

llvm-svn: 130743
 2011-05-03 00:46:49 +00:00
Eric Christopher
e637bff03a Apparently the check for direct calls is unnecessary. 
llvm-svn: 130716
 2011-05-02 20:16:33 +00:00
Eric Christopher
ad02f6c78a 80-col. 
llvm-svn: 130558
 2011-04-29 23:12:01 +00:00
Eli Friedman
996092fea3 Zap a couple now-unused functions. 
llvm-svn: 130557
 2011-04-29 22:56:48 +00:00
Eli Friedman
1940912660 Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
llvm-svn: 130552
 2011-04-29 22:48:03 +00:00
Eric Christopher
5415816eb4 Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but 
if it ever did it needs the def machinery.

llvm-svn: 130549
 2011-04-29 22:07:50 +00:00
Eric Christopher
a6fb14395f Some cleanup and optimize fallthrough more. 
llvm-svn: 130546
 2011-04-29 21:56:31 +00:00
Eli Friedman
7d05eaa3f4 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130539
 2011-04-29 21:22:56 +00:00
Eric Christopher
ba0cef1b0b Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.

llvm-svn: 130534
 2011-04-29 20:02:39 +00:00
Daniel Dunbar
c52dfd4349 MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics 
that associate sections with expressions.

llvm-svn: 130517
 2011-04-29 18:00:03 +00:00
Andrew Trick
88152ec6d2 Teach Thumb2 isel to fold and->rotr ==> ROR. 
Generalization of Nate Begeman's patch!

llvm-svn: 130502
 2011-04-29 14:18:15 +00:00
Chris Lattner
c8dff72621 use the MachineInstrBuilder operator-> to simplify some code. 
There are probably more instances of this floating around.

llvm-svn: 130474
 2011-04-29 05:24:29 +00:00
Eric Christopher
f7f8f92201 Update comments and checks to match reality. 
llvm-svn: 130464
 2011-04-29 00:07:20 +00:00
Eric Christopher
68cdb30c0d Whitespace. 
llvm-svn: 130463
 2011-04-29 00:03:10 +00:00
Eli Friedman
a93906d0c3 Revert r130454; apparently this doesn't actually work. 
llvm-svn: 130462
 2011-04-28 23:55:14 +00:00
Eli Friedman
9a80f23666 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .

llvm-svn: 130454
 2011-04-28 23:03:25 +00:00
Eric Christopher
2e9c3e61ee Be more layout aware here and swap the successor and branch condition 
if it means we get a fallthrough.

llvm-svn: 130404
 2011-04-28 16:52:09 +00:00
Eric Christopher
bea4df9acc Let the immediate leaf pattern take transforms and switch the signed 
immediate patterns in arm to using the pattern.

Handles rdar://9299434

llvm-svn: 130386
 2011-04-28 05:49:04 +00:00
Devang Patel
900ceb725b Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.

llvm-svn: 130373
 2011-04-28 02:22:40 +00:00
Kevin Enderby
dbc7221170 Fix a bug in the case that there is no add or subtract symbol and the offset 
value is zero so it does not add a NULL expr operand.

llvm-svn: 130330
 2011-04-27 21:02:27 +00:00
Devang Patel
42f4a7ff92 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
llvm-svn: 130326
 2011-04-27 20:29:27 +00:00
Jim Grosbach
77d45564c3 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019

llvm-svn: 130234
 2011-04-26 19:44:18 +00:00
Jakob Stoklund Olesen
7a2dca07a8 Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation. 
The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

llvm-svn: 130228
 2011-04-26 18:52:33 +00:00
Devang Patel
4969322bc4 Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables. 
llvm-svn: 130178
 2011-04-26 00:12:46 +00:00
Sebastian Redl
ef01c3c33f Fix Target/ARM/Thumb1FrameLowering.h header guard. 
llvm-svn: 130097
 2011-04-24 15:47:01 +00:00
Andrew Trick
a130d110d1 Thumb2 and ARM add/subtract with carry fixes. 
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).

llvm-svn: 130048
 2011-04-23 03:55:32 +00:00
Andrew Trick
31c7962ce5 whitespace 
llvm-svn: 130046
 2011-04-23 03:24:11 +00:00
Johnny Chen
dfac31bc1b Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008
 2011-04-22 19:12:43 +00:00
Devang Patel
ee6cdc52e0 Add asserts. 
llvm-svn: 129995
 2011-04-22 16:44:29 +00:00
Evan Cheng
34e8479411 In Thumb2 mode, lower frame indix references to: 
add <rd>, sp, #<imm8>
ldr <rd>, [sp, #<imm8>]
When the offset from sp is multiple of 4 and in range of 0-1020.
This saves code size by utilizing 16-bit instructions.

rdar://9321541

llvm-svn: 129971
 2011-04-22 01:42:52 +00:00
Devang Patel
692ae3cdc6 Fix DWARF description of Q registers. 
llvm-svn: 129952
 2011-04-21 23:22:35 +00:00
Devang Patel
85b3a170f5 Fix DWARF description of S registers. 
llvm-svn: 129947
 2011-04-21 22:48:26 +00:00
Devang Patel
7b613bcb4a As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF. 
llvm-svn: 129922
 2011-04-21 17:51:06 +00:00
Evan Cheng
28877b11a2 Remove -use-divmod-libcall. Let targets opt in when they are available. 
llvm-svn: 129884
 2011-04-20 22:20:12 +00:00
Jakob Stoklund Olesen
6501ea2557 Prefer cheap registers for busy live ranges. 
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

llvm-svn: 129864
 2011-04-20 18:19:48 +00:00
Stuart Hastings
1905cf10e3 Excise unintended hunk in 129858. <rdar://problem/7662569> 
llvm-svn: 129862
 2011-04-20 18:09:26 +00:00
Stuart Hastings
a552942e02 ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
llvm-svn: 129858
 2011-04-20 16:47:52 +00:00
Johnny Chen
7ceb5e40b6 Fix typo in the comment. 
llvm-svn: 129837
 2011-04-19 23:58:52 +00:00
Daniel Dunbar
1c0a0fde5c ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows() 
predicates.

llvm-svn: 129816
 2011-04-19 21:14:45 +00:00
Eric Christopher
21ad2325df Remove some duplicate op action entries and reorganize. 
llvm-svn: 129781
 2011-04-19 18:49:19 +00:00