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17870 Commits

Author SHA1 Message Date
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Rafael Espindola
707fa44bc0 Add 132187 back now that the real problem is fixed. 
llvm-svn: 132238
 2011-05-28 00:24:37 +00:00
Cameron Zwarich
cd3c1b5829 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

llvm-svn: 132235
 2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
93eae0fd19 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb 
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

llvm-svn: 132233
 2011-05-27 23:46:09 +00:00
Rafael Espindola
8ed6285c8d It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check. 
llvm-svn: 132230
 2011-05-27 23:36:02 +00:00
Cameron Zwarich
ded03d4e24 Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass() 
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

llvm-svn: 132225
 2011-05-27 22:26:04 +00:00
Rafael Espindola
2230168a0f Make size computation less brittle. 
llvm-svn: 132222
 2011-05-27 22:05:41 +00:00
Evan Cheng
0fcb465bab Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
llvm-svn: 132211
 2011-05-27 20:11:27 +00:00
Jakob Stoklund Olesen
021b1ff0c7 Delete MethodBodies that only filtered reserved registers. 
The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.

llvm-svn: 132199
 2011-05-27 18:27:13 +00:00
Eli Friedman
560532051b Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 
llvm-svn: 132194
 2011-05-27 18:02:04 +00:00
Rafael Espindola
c74e8fda1f Remove DwarfRegNum from the individual bits of the condition register. 
These should be DW_OP_bit_piece of CR (64).

llvm-svn: 132192
 2011-05-27 16:15:27 +00:00
Rafael Espindola
a275f4cfc7 Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece. 
llvm-svn: 132190
 2011-05-27 16:01:08 +00:00
Rafael Espindola
7e68d3bf57 Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to 
refer to them.

I tested this with both check-all and the gdb testsuite.

llvm-svn: 132187
 2011-05-27 15:08:24 +00:00
Eric Christopher
0e12efbed1 Make the branch encoding for tBcc more obvious that it's a 4-byte opcode 
followed by a conditional and imm8.

llvm-svn: 132179
 2011-05-27 03:50:53 +00:00
Eric Christopher
cfce589451 Fix comment. 
llvm-svn: 132178
 2011-05-27 03:46:51 +00:00
Chad Rosier
b87c4a6945 Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. 
crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].

llvm-svn: 132163
 2011-05-26 23:13:19 +00:00
Akira Hatanaka
71839b355d Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if 
a function has any function calls.

llvm-svn: 132140
 2011-05-26 20:30:31 +00:00
Rafael Espindola
a77d692299 Fix some dwarf register numbers. 
llvm-svn: 132136
 2011-05-26 19:25:47 +00:00
Akira Hatanaka
5bfbea9ef2 Add support for C++ exception handling. 
llvm-svn: 132131
 2011-05-26 18:59:03 +00:00
Eric Christopher
4fc5b88850 Reorganize these slightly according to operand type. 
llvm-svn: 132128
 2011-05-26 18:22:26 +00:00
Akira Hatanaka
5a8bd76f99 Set HasSetDirective to true. 
llvm-svn: 132127
 2011-05-26 18:16:18 +00:00
Stuart Hastings
837a958ff6 Reverting 132105: it broke some LLVM-GCC DejaGNU tests. 
llvm-svn: 132108
 2011-05-26 04:09:49 +00:00
Cameron Zwarich
9c871755b6 Mark tBX as an indirect branch rather than a return. 
llvm-svn: 132107
 2011-05-26 03:41:12 +00:00
Stuart Hastings
e704bfb21e Correctly handle a one-word struct passed byval on x86_64. 
rdar://problem/6920088

llvm-svn: 132105
 2011-05-26 02:44:56 +00:00
Eli Friedman
93ffb875ad Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099
 2011-05-25 23:49:02 +00:00
Akira Hatanaka
3f49cbeb37 Define WeakRefDirective. 
llvm-svn: 132098
 2011-05-25 23:30:30 +00:00
Cameron Zwarich
9c19995747 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
llvm-svn: 132086
 2011-05-25 21:53:50 +00:00
Eric Christopher
e02bd15dbc Clean up comment a bit. 
llvm-svn: 132083
 2011-05-25 21:19:19 +00:00
Eric Christopher
807da21e47 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939

llvm-svn: 132081
 2011-05-25 20:51:58 +00:00
Akira Hatanaka
4806508364 Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already 
been defined in MipsInstrFPU.td.

llvm-svn: 132076
 2011-05-25 20:08:05 +00:00
Akira Hatanaka
32b5043265 Custom-lower FCOPYSIGN nodes. 
llvm-svn: 132074
 2011-05-25 19:32:07 +00:00
Eli Friedman
2bdd096540 Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values. 
llvm-svn: 132073
 2011-05-25 19:09:45 +00:00
Akira Hatanaka
ae2e2d557a Update MaxCallFrameSize regardless of the relocation model selected. 
llvm-svn: 132070
 2011-05-25 18:08:32 +00:00
Akira Hatanaka
953e0a3c45 Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should 
return 0 if there are no function calls made. 

llvm-svn: 132065
 2011-05-25 17:52:48 +00:00
Akira Hatanaka
33415b8179 Coding style fixes. Added comments. 
llvm-svn: 132063
 2011-05-25 17:32:06 +00:00
Francois Pichet
b2042fbfe2 Remove unused OpcodeMask enumerator. 
llvm-svn: 132062
 2011-05-25 17:02:53 +00:00
Francois Pichet
fab3c58733 Fix MSVC warning: "is out of range for enum constant" 
MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.

llvm-svn: 132057
 2011-05-25 15:58:10 +00:00
Cameron Zwarich
5c410bd5f6 Restore an accidentally removed comment. 
llvm-svn: 132044
 2011-05-25 04:48:17 +00:00
Cameron Zwarich
4f47b296d8 Move some code to a more logical place. 
llvm-svn: 132043
 2011-05-25 04:45:29 +00:00
Cameron Zwarich
beae5f20e8 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

llvm-svn: 132042
 2011-05-25 04:45:27 +00:00
Cameron Zwarich
5a32e53e3f Change the order of tBX's operands so that the predicate operands come after the 
target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

llvm-svn: 132041
 2011-05-25 04:45:23 +00:00
Cameron Zwarich
08753a605b Rename tBX_Rm to tBX. 
llvm-svn: 132040
 2011-05-25 04:45:20 +00:00
Cameron Zwarich
d9707488bb Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
 2011-05-25 04:45:14 +00:00
Rafael Espindola
70213c7c5f Replace the -unwind-tables option with a per function flag. This is more 
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

llvm-svn: 132033
 2011-05-25 03:44:17 +00:00
Akira Hatanaka
a5b11ee449 Fix lowering of DYNAMIC_STACKALLOC nodes. 
llvm-svn: 132030
 2011-05-25 02:20:00 +00:00
Bruno Cardoso Lopes
3a4aae57f4 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026
 2011-05-25 00:35:03 +00:00
Eric Christopher
4f193f9555 Implement the arm 'L' asm modifier. 
Part of rdar://9119939

llvm-svn: 132024
 2011-05-24 23:27:13 +00:00
Eric Christopher
a6d7ccb170 Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939

llvm-svn: 132023
 2011-05-24 23:15:43 +00:00
Eric Christopher
4783e5e316 Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.

llvm-svn: 132015
 2011-05-24 22:27:43 +00:00
Eric Christopher
03965fa3b6 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657

llvm-svn: 132011
 2011-05-24 22:10:34 +00:00