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7100 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
709699b8d3 Initial Mips support, here we go! =) 
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
 2007-06-06 07:42:06 +00:00
Evan Cheng
886c1f49ca Print predicate of the second instruction of the two-piece constant MI. 
llvm-svn: 37437
 2007-06-05 18:55:18 +00:00
Evan Cheng
820e352652 PIC label asm printing cosmetic changes. 
llvm-svn: 37434
 2007-06-05 07:36:38 +00:00
Evan Cheng
fdfe615197 Misuse of hasExternalLinkage(), should be checking isDeclaration(). 
llvm-svn: 37419
 2007-06-04 18:54:57 +00:00
Chris Lattner
8a38eebb69 update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400
 2007-06-02 18:45:14 +00:00
Evan Cheng
8a52b80cdf Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
llvm-svn: 37388
 2007-06-01 20:51:29 +00:00
Evan Cheng
8589b95a33 Set ARM ifcvt duplication limit to 3 for now. 
llvm-svn: 37385
 2007-06-01 08:28:59 +00:00
Evan Cheng
c2fec89f4a Make jumptable non-predicable for now. 
llvm-svn: 37381
 2007-06-01 00:56:15 +00:00
Chris Lattner
72e07238ba Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373
 2007-05-31 18:57:45 +00:00
Evan Cheng
3672d15956 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
llvm-svn: 37351
 2007-05-29 23:34:19 +00:00
Evan Cheng
5df14b3451 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
llvm-svn: 37349
 2007-05-29 23:32:06 +00:00
Evan Cheng
ff31eed2be Add missing const qualifiers. 
llvm-svn: 37342
 2007-05-29 18:42:18 +00:00
Evan Cheng
d8b25a2091 Add missing const qualifiers. 
llvm-svn: 37341
 2007-05-29 18:35:22 +00:00
Nicolas Geoffray
fff14eecb5 Implementation of compilation callback in PPC ELF32 
llvm-svn: 37340
 2007-05-29 16:33:18 +00:00
Dan Gohman
1b1932dda5 Add explicit qualification for namespace MVT members. 
llvm-svn: 37320
 2007-05-24 14:33:05 +00:00
Evan Cheng
80122ab529 Hooks for predication support. 
llvm-svn: 37308
 2007-05-23 07:22:05 +00:00
Evan Cheng
9f763bd3fd Rename a parameter. 
llvm-svn: 37307
 2007-05-23 07:21:11 +00:00
Dale Johannesen
738f94210c name change requested by review of previous patch 
llvm-svn: 37289
 2007-05-22 18:31:04 +00:00
Dale Johannesen
fe0fe14411 Make tail merging the default, except on powerPC. There was no prior art 
for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285
 2007-05-22 17:14:46 +00:00
Bill Wendling
26eb9fb1e0 We only need to specify the most-implied feature for an architecture. 
llvm-svn: 37275
 2007-05-22 05:15:37 +00:00
Evan Cheng
f448047ec2 Fix some -march=thumb regressions. tBR_JTr is not predicable. 
llvm-svn: 37272
 2007-05-21 23:17:32 +00:00
Dale Johannesen
f01566b705 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
llvm-svn: 37271
 2007-05-21 22:42:04 +00:00
Dale Johannesen
8f484d16b0 Add some patterns for PIC PC-relative loads and stores. 
llvm-svn: 37269
 2007-05-21 22:14:33 +00:00
Evan Cheng
d173398eee BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
llvm-svn: 37268
 2007-05-21 18:56:31 +00:00
Evan Cheng
3f386274c0 BlockHasNoFallThrough() now returns true if block ends with a return instruction. 
llvm-svn: 37266
 2007-05-21 18:44:17 +00:00
Dan Gohman
875f6bde73 Apply this patch: 
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html

llvm-svn: 37240
 2007-05-18 23:21:46 +00:00
Chris Lattner
a7834d79a0 add a note 
llvm-svn: 37239
 2007-05-18 20:18:14 +00:00
Dan Gohman
ec87afe526 Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE. 
llvm-svn: 37234
 2007-05-18 18:44:07 +00:00
Evan Cheng
e875732104 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
llvm-svn: 37199
 2007-05-18 01:53:54 +00:00
Evan Cheng
03349b0344 Silence some compilation warnings. 
llvm-svn: 37197
 2007-05-18 01:19:57 +00:00
Evan Cheng
2fc338fac1 Set ARM if-conversion block size threshold to 10 instructions for now. 
llvm-svn: 37194
 2007-05-18 00:19:34 +00:00
Evan Cheng
90b0ff05f6 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
llvm-svn: 37193
 2007-05-18 00:18:17 +00:00
Evan Cheng
234aab208a RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
llvm-svn: 37192
 2007-05-18 00:05:48 +00:00
Dale Johannesen
f66c6b85f1 More effective breakdown of memcpy into repeated load/store. These are now 
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179
 2007-05-17 21:31:21 +00:00
Evan Cheng
1b4af5f975 Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector. 
llvm-svn: 37173
 2007-05-17 18:45:50 +00:00
Evan Cheng
9c4e69e6e5 Added missing patterns for UNPCKH* and PUNPCKH*. 
llvm-svn: 37172
 2007-05-17 18:44:37 +00:00
Chris Lattner
9a53871650 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't 
cause other regressions.

llvm-svn: 37160
 2007-05-17 17:13:13 +00:00
Anton Korobeynikov
375cafc275 Revert patch for PR1427. It breaks almost all vector tests. 
llvm-svn: 37159
 2007-05-17 07:50:14 +00:00
Chris Lattner
a18b7d76b3 add support for 128-bit add/sub on ppc64 
llvm-svn: 37158
 2007-05-17 06:52:46 +00:00
Chris Lattner
307a29e831 add support for 128-bit integer add/sub 
llvm-svn: 37154
 2007-05-17 06:35:11 +00:00
Chris Lattner
f65fe1d931 Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll 
llvm-svn: 37141
 2007-05-17 03:29:42 +00:00
Evan Cheng
dc9e574073 Remove. Not needed. 
llvm-svn: 37139
 2007-05-17 00:11:35 +00:00
Evan Cheng
4fa2db30d9 Default implementation of TargetInstrInfo::getBlockSize(). 
llvm-svn: 37138
 2007-05-16 23:53:44 +00:00
Evan Cheng
b09bf9914f ARM::tB is also predicable. 
llvm-svn: 37125
 2007-05-16 21:53:43 +00:00
Evan Cheng
973f4a19cb PredicateInstruction returns true if the operation was successful. 
llvm-svn: 37124
 2007-05-16 21:53:07 +00:00
Evan Cheng
30f3168b7b Add default implementation of PredicateInstruction(). 
llvm-svn: 37123
 2007-05-16 21:20:37 +00:00
Evan Cheng
48f230dcb0 Move if-conversion after all passes that may use register scavenger. 
llvm-svn: 37120
 2007-05-16 20:52:46 +00:00
Evan Cheng
f7a017dfa7 Removed isPredicable(). 
llvm-svn: 37119
 2007-05-16 20:50:23 +00:00
Evan Cheng
d3f1a259db Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
llvm-svn: 37118
 2007-05-16 20:50:01 +00:00
Evan Cheng
0aced52f41 Added isPredicable bit to class Instruction. 
llvm-svn: 37117
 2007-05-16 20:47:01 +00:00