Commit Graph

140035 Commits

Author SHA1 Message Date
Teresa Johnson
26a0340c9b [ThinLTO] Use NoPromote flag in summary during promotion
Summary:
Replace the check of whether a GV has a section with the flag check
in the summary. This is in preparation for using the NoPromote flag
to convey other situations when we can't promote (e.g. locals used in
inline asm).

Reviewers: mehdi_amini

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26063

llvm-svn: 285507
2016-10-29 21:31:48 +00:00
Peter Collingbourne
87247f2c07 IR: Remove a no longer needed assert.
This assert was checking for a miscompile in a version of GCC that
we no longer support.

llvm-svn: 285506
2016-10-29 20:57:12 +00:00
Craig Topper
693d21e48c [X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy intrinsics can select EVEX encoded instructions when available.
This requires a minor rename of the instructions due to the use of different tablegen classes and how the names are concatenated.

llvm-svn: 285501
2016-10-29 18:41:45 +00:00
Sanjay Patel
c3d6bced70 [ValueTracking] recognize more variants of smin/smax
Try harder to detect obfuscated min/max patterns: the initial pattern was added with D9352 / rL236202. 
There was a bug fix for PR27137 at rL264996, but I think we can do better by folding the corresponding
smax pattern and commuted variants.

The codegen tests demonstrate the effect of ValueTracking on the backend via SelectionDAGBuilder. We
can't expose these differences minimally in IR because we don't have smin/smax intrinsics for IR.

Differential Revision: https://reviews.llvm.org/D26091

llvm-svn: 285499
2016-10-29 16:21:19 +00:00
Sanjay Patel
7c8d8c8822 [x86] add tests for smin/smax matchSelPattern (D26091)
llvm-svn: 285498
2016-10-29 16:02:57 +00:00
Sanjay Patel
d37ca92dd0 [InstCombine] re-use bitcasted compare operands in selects (PR28001)
These mixed bitcast patterns show up with SSE/AVX intrinsics because we bitcast function parameters to <2 x i64>.

The bitcasts obfuscate the expected min/max forms as shown in PR28001:
https://llvm.org/bugs/show_bug.cgi?id=28001#c6

Differential Revision: https://reviews.llvm.org/D25943

llvm-svn: 285495
2016-10-29 15:22:04 +00:00
Simon Pilgrim
483654e906 [DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits
Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements.

This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.

The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used.

I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course.

DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit.

This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander!

Differential Revision: https://reviews.llvm.org/D25691

llvm-svn: 285494
2016-10-29 11:29:39 +00:00
Elena Demikhovsky
c869a69914 Fixed FMA + FNEG combine.
Masked form of FMA should be omitted in this optimization.

Differential Revision: https://reviews.llvm.org/D25984

llvm-svn: 285492
2016-10-29 08:44:46 +00:00
Matt Arsenault
3ee7b5cf1b AMDGPU: Use 1/2pi inline imm on VI
I'm guessing at how it is supposed to be printed

llvm-svn: 285490
2016-10-29 04:05:06 +00:00
Matthias Braun
6de13f8bcf AArch64DeadRegisterDefinitionsPass: Cleanup; NFC
- Fix doxygen file comment
- reduce indentation in loop
- Factor out some common subexpressions
- Move independent helper function out of class
- Fix Changed flag (this is not strictly NFC but a bugfix, but the flag
  seems ignored anyway)

llvm-svn: 285488
2016-10-29 01:03:41 +00:00
Rui Ueyama
ee986aa4c9 Define calculateDbgStreamSize for consistency.
llvm-svn: 285487
2016-10-29 00:56:44 +00:00
Tim Shen
9e6b8a7f7a [APFloat] Remove the redundent function body of uninitialized ctor, which should be done in r285468
llvm-svn: 285486
2016-10-29 00:51:41 +00:00
Zachary Turner
ffabf1c406 Resubmit "Add support for advanced number formatting."
This resubmits r284436 and r284437, which were reverted in
r284462 as they were breaking the AArch64 buildbot.

The breakage on AArch64 turned out to be a miscompile which is
still not fixed, but is actively tracked at llvm.org/pr30748.

This resubmission re-writes the code in a way so as to make the
miscompile not happen.

llvm-svn: 285483
2016-10-29 00:27:22 +00:00
Rui Ueyama
c91ba4c121 Do not print out Flags field twice.
llvm-svn: 285481
2016-10-28 23:57:37 +00:00
Davide Italiano
0958ae681a [DAGCombiner] Fix a crash visiting AND nodes.
Instead of asserting that the shift count is != 0 we just bail out
as it's not profitable trying to optimize a node which will be
removed anyway.

Differential Revision:  https://reviews.llvm.org/D26098

llvm-svn: 285480
2016-10-28 23:55:32 +00:00
Tom Stellard
94e161c5b2 AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions
Summary:
Flat instruction can return out of order, so we need always need to wait
for all the outstanding flat operations.

Reviewers: tony-tye, arsenm

Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D25998

llvm-svn: 285479
2016-10-28 23:53:48 +00:00
Matt Arsenault
f557c5ed41 AMDGPU: Fix instruction flags for s_endpgm
Set isReturn, remove hasSideEffects. Also remove
hasCtrlDep, I'm not really sure what that does.

llvm-svn: 285476
2016-10-28 23:00:38 +00:00
Adrian Prantl
131b3bf6d0 Refactor DW_LNE_* into Dwarf.def
llvm-svn: 285475
2016-10-28 22:57:02 +00:00
Adrian Prantl
e918422a2f Refactor DW_LNS_* into Dwarf.def
llvm-svn: 285474
2016-10-28 22:56:59 +00:00
Adrian Prantl
1bba28d9b8 Refactor DW_APPLE_PROPERTY_* into Dwarf.def
llvm-svn: 285473
2016-10-28 22:56:56 +00:00
Adrian Prantl
b7bf05aced Refactor DW_CFA_* into Dwarf.def
llvm-svn: 285472
2016-10-28 22:56:53 +00:00
Adrian Prantl
343b869dc9 Remove whitespace
llvm-svn: 285471
2016-10-28 22:56:50 +00:00
Adrian Prantl
0c3b1e3820 Refactor all DW_FORM_* constants into Dwarf.def
llvm-svn: 285470
2016-10-28 22:56:45 +00:00
Tim Shen
024b1d6019 [APFloat] Fix memory bugs revealed by MSan
Reviewers: eugenis, hfinkel, kbarton, iteratee, echristo

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D26102

llvm-svn: 285468
2016-10-28 22:45:33 +00:00
Justin Bogner
6d1d2115c5 SDAG: Make sure we use an allocatable reg class when we create this vreg
As per the discussion on r280783, if constrainRegClass fails we need
to call getAllocatableClass like we did before that commit.

llvm-svn: 285467
2016-10-28 22:42:54 +00:00
Kostya Serebryany
2ba6420696 [libFuzzer] mention one more trophie
llvm-svn: 285465
2016-10-28 22:03:54 +00:00
Justin Lebar
416f04c060 Add missing lit.local.cfg to llvm/test/Transforms/CodeGenPrepare/NVPTX.
llvm-svn: 285464
2016-10-28 21:56:07 +00:00
Matt Arsenault
a0090a0113 AMDGPU: Add definitions for scalar store instructions
Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.

llvm-svn: 285463
2016-10-28 21:55:15 +00:00
Matt Arsenault
342b4f2c0e AMDGPU: Rename glc operand type
While trying to add the glc bit to SMEM instructions on VI
with the new refactoring I ran into some kind of shadowing
problem for the glc operand when using the pseudoinstruction
as a multiclass parameter.

Everywhere that currently uses it defines the operand to have the same
name as its type, i.e. glc:$glc which works. For some reason now it
conflicts, and its up evaluating to the wrong thing. For the
real encoding classes,

let Inst{16} = !if(ps.has_glc, glc, ?); was not being evaluated
and still visible in the Inst initializer in the expanded td file.
In other cases I got a a different error about an illegal operand
where this was using { 0 } initializer from the bits<1> glc initializer
instead of evaluating it as false in the if.

For consistency all of the operand types should probably
be captialized to avoid conflicting with the variable names
unless somebody has a better idea of how to fix this.

llvm-svn: 285462
2016-10-28 21:55:08 +00:00
Justin Lebar
50ae991af5 [NVPTX] Compute 'rem' using the result of 'div', if possible.
Summary:
In isel, transform

  Num % Den

into

  Num - (Num / Den) * Den

if the result of Num / Den is already available.

Reviewers: tra

Subscribers: hfinkel, llvm-commits, jholewinski

Differential Revision: https://reviews.llvm.org/D26090

llvm-svn: 285461
2016-10-28 21:44:00 +00:00
Justin Lebar
188600d04d Don't leave unused divs/rems sitting around in BypassSlowDivision.
Summary:
This "pass" eagerly creates div and rem instructions even when only one
is needed -- it relies on a later pass (machine DCE?) to clean them up.

This is problematic not just from a cleanliness perspective (this pass
is running during CodeGenPrepare, so should leave the IR in a better
state), but it also creates a problem for instruction selection.  If we
always have a div+rem, isel will always select a divrem instruction (if
possible), even when a single div or rem would do.

Specifically, in NVPTX, we want to compute rem from the output of div,
if available.  But if a div is not available, we want to leave the rem
alone.  This transformation is overeager if div is always available.

Because this code runs as part of CodeGenPrepare, it's nontrivial to
write a test for this change.  But this will effectively be tested by
a later patch which adds the aforementioned change to NVPTX isel.

Reviewers: tra

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26088

llvm-svn: 285460
2016-10-28 21:43:54 +00:00
Justin Lebar
b61890b5fc Don't claim the udiv created in BypassSlowDivision is exact.
Summary:
In BypassSlowDivision's short-dividend path, we would create e.g.

  udiv exact i32 %a, %b

"exact" here means that we are asserting that %a is a multiple of %b.
But we have no reason to believe this must be true -- this is just a
bug, as far as I can tell.

Reviewers: tra

Subscribers: jholewinski, llvm-commits

Differential Revision: https://reviews.llvm.org/D26097

llvm-svn: 285459
2016-10-28 21:43:51 +00:00
Justin Bogner
5e2e245a64 cmake: Enable the lto cache when building with -flto=thin on darwin
llvm-svn: 285450
2016-10-28 20:48:47 +00:00
Matt Arsenault
4dd60033c4 AMDGPU: Change check prefix in test
llvm-svn: 285449
2016-10-28 20:33:01 +00:00
Adrian Prantl
d6ecbca519 Fix a copy&paste error in the macro definition for HANDLE_DW_MACRO and
HANDLE_DE_RLE. Caught by the LLDB build bot.

llvm-svn: 285448
2016-10-28 20:32:17 +00:00
Matt Arsenault
d438707f8d AMDGPU: Diagnose using too many SGPRs
This is possible when using inline asm.

llvm-svn: 285447
2016-10-28 20:31:47 +00:00
Adrian Prantl
53604bc312 Remove redundant prefixes from constants and unbreak the LLDB bots.
llvm-svn: 285444
2016-10-28 20:18:26 +00:00
Tim Shen
cd2f24facc [APFloat] Use std::move() in move assignment operator
llvm-svn: 285442
2016-10-28 20:13:06 +00:00
Krzysztof Parzyszek
f25ba8d356 Handle non-~0 lane masks on live-in registers in LivePhysRegs
When LivePhysRegs adds live-in registers, it recognizes ~0 as a special
lane mask indicating the entire register. If the lane mask is not ~0,
it will only add the subregisters that overlap the specified lane mask.

The problem is that if a live-in register does not have subregisters,
and the lane mask is not ~0, it will not be added to the live set.
(The given lane mask may simply be the lane mask of its register class.)

If a register does not have subregisters, add it to the live set if
the lane mask is non-zero.

Differential Revision: https://reviews.llvm.org/D26094

llvm-svn: 285440
2016-10-28 20:06:37 +00:00
Matt Arsenault
c44a8a92e5 SpeculativeExecution: Allow speculating more inst types
Partial step towards removing the whitelist and only
using TTI's cost.

llvm-svn: 285438
2016-10-28 20:00:33 +00:00
Matt Arsenault
0536acc73b AMDGPU: Fix using incorrect private resource with no allocation
It's possible to have a use of the private resource descriptor or
scratch wave offset registers even though there are no allocated
stack objects. This would result in continuing to use the maximum
number reserved registers. This could go over the number of SGPRs
available on VI, or violate the SGPR limit requested by
the function attributes.

llvm-svn: 285435
2016-10-28 19:43:31 +00:00
Nemanja Ivanovic
2304e2b9df Implement vector count leading/trailing bytes with zero lsb and vector parity
builtins - llvm portion

This patch corresponds to review https://reviews.llvm.org/D26003.
Committing on behalf of Zaara Syeda.

llvm-svn: 285434
2016-10-28 19:38:24 +00:00
Teresa Johnson
3d8292c60a [ThinLTO] Use flags from summary when writing variable summary (NFC)
We already read the flags out of the summary when writing the summary
records for functions and aliases, do the same for variables.

This is an NFC change for now since the flags computed on the fly from
the GlobalValue currently will always match those in the summary
already, but once I send a follow-on patch to set the NoRename flag for
locals in the llvm.used set this becomes a necessary change.

llvm-svn: 285433
2016-10-28 19:36:00 +00:00
George Burgess IV
406ed15c52 [MemorySSA] Add const to getClobberingMemoryAccess.
Thanks to bryant for the patch!

Differential Revision: https://reviews.llvm.org/D26086

llvm-svn: 285432
2016-10-28 19:22:46 +00:00
Arnold Schwaighofer
252873258a Make swift calling convention test specific to armv7
llvm-svn: 285431
2016-10-28 19:18:09 +00:00
Sanjay Patel
b6db7ed06e [x86] add tests for missed umin/umax
This is actually a deficiency in ValueTracking's matchSelectPattern(),
but a codegen test is the simplest way to expose the bug.

llvm-svn: 285429
2016-10-28 19:08:20 +00:00
Lang Hames
ff2bdd0394 [Error] Unify +Asserts/-Asserts behavior for checked flags in Error/Expected<T>.
(1) Switches to raw pointer and bitmasking operations for Error payload.
(2) Always includes the 'unchecked' bitfield in Expected<T>, even in -Asserts.
(3) Always propagates checked bit status in move-ops for both classes, even in
    -Asserts.

This should allow debug programs to link against release libraries without
encountering spurious 'unchecked error' terminations.

Error checks still aren't verified in release mode so this doesn't introduce
any new control flow, but it does require new bit-masking ops in release mode
to preserve the flag values during move ops. I expect the overhead to be
minimal, but if we discover any corner cases where it matters we could fix
this by making flag propagation conditional on a new build option.

llvm-svn: 285426
2016-10-28 18:24:15 +00:00
Adrian Prantl
9f0ded5064 Move the DWARF attribute constants into Dwarf.def and delete 300 lines of silly code.
llvm-svn: 285425
2016-10-28 18:21:39 +00:00
Matthias Braun
fcada89b82 MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC
llvm-svn: 285423
2016-10-28 18:05:09 +00:00
Matthias Braun
b3cd5f40cd TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.
TargetPassConfig::addMachinePasses() does some housekeeping first:
Handling the -print-machineinstrs flag and doing an initial printing
"After Instruction Selection". There is no reason for RegUsageInfoProp
to run before those two steps.

llvm-svn: 285422
2016-10-28 18:05:05 +00:00