RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-15 06:01:20 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
43,196 Commits 6 Branches 6 Tags
Commit Graph

83 Commits

Author SHA1 Message Date
Evan Cheng
9f23724d53 Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. 
llvm-svn: 37484
 2007-06-07 01:37:54 +00:00
Evan Cheng
ff31eed2be Add missing const qualifiers. 
llvm-svn: 37342
 2007-05-29 18:42:18 +00:00
Evan Cheng
80122ab529 Hooks for predication support. 
llvm-svn: 37308
 2007-05-23 07:22:05 +00:00
Evan Cheng
f448047ec2 Fix some -march=thumb regressions. tBR_JTr is not predicable. 
llvm-svn: 37272
 2007-05-21 23:17:32 +00:00
Evan Cheng
d173398eee BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
llvm-svn: 37268
 2007-05-21 18:56:31 +00:00
Evan Cheng
90b0ff05f6 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
llvm-svn: 37193
 2007-05-18 00:18:17 +00:00
Evan Cheng
973f4a19cb PredicateInstruction returns true if the operation was successful. 
llvm-svn: 37124
 2007-05-16 21:53:07 +00:00
Evan Cheng
f7a017dfa7 Removed isPredicable(). 
llvm-svn: 37119
 2007-05-16 20:50:23 +00:00
Evan Cheng
34928ae31f Hooks for predication support. 
llvm-svn: 37093
 2007-05-16 02:01:49 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Dale Johannesen
7c3b78cf98 Rewrite of Thumb constant islands handling (exact allowance for padding 
around islands and jump tables).

llvm-svn: 36573
 2007-04-29 19:19:30 +00:00
Evan Cheng
eff332e3e1 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
llvm-svn: 36483
 2007-04-26 19:00:32 +00:00
Evan Cheng
de9468373e Relex assertions to account for additional implicit def / use operands. 
llvm-svn: 36430
 2007-04-25 07:12:14 +00:00
Anton Korobeynikov
f3e62a428a Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Evan Cheng
16696f0ad8 Inverted logic. 
llvm-svn: 35619
 2007-04-03 06:44:25 +00:00
Evan Cheng
968135bd3f findRegisterUseOperand() changed. 
llvm-svn: 35366
 2007-03-26 22:41:48 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
60bde0ebb1 Spill / restore should avoid modifying the condition register. 
llvm-svn: 33971
 2007-02-07 00:06:56 +00:00
Evan Cheng
5e0f0364d0 Copy and paste bug. 
llvm-svn: 33658
 2007-01-30 08:22:33 +00:00
Evan Cheng
78628c7f32 Misseed thumb jumptable branch. 
llvm-svn: 33656
 2007-01-30 08:03:06 +00:00
Evan Cheng
171943e26e Factor GetInstSize() out of constpool island pass. 
llvm-svn: 33644
 2007-01-29 23:45:17 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Rafael Espindola
2259fab5cf fix warning about missing newline at end of file 
llvm-svn: 31162
 2006-10-24 17:07:11 +00:00
Chris Lattner
71dc932fcb implement uncond branch insertion, mark branches with isBranch. 
llvm-svn: 31160
 2006-10-24 16:47:57 +00:00
Rafael Espindola
1a3020bfcf add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Rafael Espindola
89ac048c5d partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
ae2d1c53c7 change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola
071c83dff0 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6 handle the "mov reg1, reg2" case in isMoveInstr 
llvm-svn: 28945
 2006-06-27 21:52:45 +00:00
Rafael Espindola
bb1e2e2c52 implement minimal versions of 
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr

llvm-svn: 28431
 2006-05-23 02:48:20 +00:00
Rafael Espindola
dd49dfc0df added a skeleton of the ARM backend 
llvm-svn: 28301
 2006-05-14 22:18:28 +00:00