58 Commits

Author SHA1 Message Date
Evan Cheng
3c0113820b Fix pre- and post-indexed load / store encoding bugs.
llvm-svn: 59230
2008-11-13 07:34:59 +00:00
Evan Cheng
a4dc0e304e Fix address mode 3 immediate offset mode encoding.
llvm-svn: 59109
2008-11-12 07:34:37 +00:00
Evan Cheng
7fef8cfe75 Consolidate formats; fix FCMPED etc. encodings.
llvm-svn: 59107
2008-11-12 07:18:38 +00:00
Evan Cheng
0966883093 Fix VFP conversion instruction encodings.
llvm-svn: 59104
2008-11-12 06:41:41 +00:00
Evan Cheng
8b7fefc126 Fix FMDRR encoding.
llvm-svn: 59088
2008-11-11 22:46:12 +00:00
Evan Cheng
35f1477c5a Encode VFP load / store instructions.
llvm-svn: 59084
2008-11-11 21:48:44 +00:00
Evan Cheng
91e4ef91c5 Encode VFP conversion instructions.
llvm-svn: 59074
2008-11-11 19:40:26 +00:00
Evan Cheng
3c62bb7471 Encode VFP arithmetic instructions.
llvm-svn: 59016
2008-11-11 02:11:05 +00:00
Evan Cheng
88726d85eb Encode misc arithmetic instructions.
llvm-svn: 58828
2008-11-07 01:41:35 +00:00
Evan Cheng
3bcb71912f Encode extend instructions; more clean up.
llvm-svn: 58818
2008-11-06 22:15:19 +00:00
Evan Cheng
af54e4ed18 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
2008-11-06 17:48:05 +00:00
Evan Cheng
aa24d19533 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
llvm-svn: 58800
2008-11-06 08:47:38 +00:00
Evan Cheng
078361bddc Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
llvm-svn: 58793
2008-11-06 03:35:07 +00:00
Evan Cheng
ca6759021b Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
Evan Cheng
9970c31dcf Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
llvm-svn: 58764
2008-11-05 18:35:52 +00:00
Jim Grosbach
5262898365 Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
llvm-svn: 58626
2008-11-03 18:38:31 +00:00
Dan Gohman
86527c1834 Const-ify several TargetInstrInfo methods.
llvm-svn: 57622
2008-10-16 01:49:15 +00:00
Jim Grosbach
5fb8bb7434 need ARM.h for ARMCC definition
llvm-svn: 57261
2008-10-07 21:01:51 +00:00
Jim Grosbach
d44d20be6e Encode the conditional execution predicate when JITing.
llvm-svn: 57258
2008-10-07 19:05:35 +00:00
Evan Cheng
0a3a595612 Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng
18fd8337b3 Eliminate unnecessary instruction formats.
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng
adf6720626 Rewrite address mode 1 code emission routines.
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
Owen Anderson
5fef19facf Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Owen Anderson
600a8ca0d5 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
Owen Anderson
604f9f722d Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058
2008-07-02 23:41:07 +00:00
Dan Gohman
f9d5689496 Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091
2008-05-14 01:58:56 +00:00
Nicolas Geoffray
82baa2d2c6 Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Evan Cheng
38a755499d Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Dan Gohman
2b96ce84aa Add explicit keywords.
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Dan Gohman
cabaec582f Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Evan Cheng
90f03a0b88 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Owen Anderson
f19692b2f6 Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Owen Anderson
2adf8c5533 Move some more functionality from MRegisterInfo to TargetInstrInfo.
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Owen Anderson
e6856128ab Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
1285ec2ae7 Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
ae7e2c1e03 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Christopher Lamb
7f21e45b06 Fix a misnamed parameter.
llvm-svn: 43145
2007-10-18 19:29:45 +00:00
Raul Herbster
ffa8296e3f Instruction formats added used to generate multiply instructions of V5TE.
llvm-svn: 41629
2007-08-30 23:34:14 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster.
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng
e6d0631c68 Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
llvm-svn: 37606
2007-06-15 21:15:00 +00:00
Evan Cheng
ff31eed2be Add missing const qualifiers.
llvm-svn: 37342
2007-05-29 18:42:18 +00:00
Evan Cheng
80122ab529 Hooks for predication support.
llvm-svn: 37308
2007-05-23 07:22:05 +00:00
Evan Cheng
90b0ff05f6 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
Evan Cheng
973f4a19cb PredicateInstruction returns true if the operation was successful.
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
Evan Cheng
f7a017dfa7 Removed isPredicable().
llvm-svn: 37119
2007-05-16 20:50:23 +00:00