Commit Graph

166799 Commits

Author SHA1 Message Date
Serge Guelton
478934d29a Use std::reference_wrapper instead of llvm::ReferenceStorage
Reviewed By: Bigcheese
Differential Revision: https://reviews.llvm.org/D49298

llvm-svn: 337444
2018-07-19 09:24:34 +00:00
Simon Pilgrim
baaeb99adf Fix spelling mistake in comments. NFCI.
llvm-svn: 337442
2018-07-19 09:14:39 +00:00
Max Kazantsev
78e21c99d5 [SCEV] Fix buggy behavior in getAddExpr with truncs
SCEV tries to constant-fold arguments of trunc operands in SCEVAddExpr, and when it does
that, it passes wrong flags into the recursion. It is only valid to pass flags that are proved for
narrow type into a computation in wider type if we can prove that trunc instruction doesn't
actually change the value. If it did lose some meaningful bits, we may end up proving wrong
no-wrap flags for sum of arguments of trunc.

In the provided test we end up with `nuw` where it shouldn't be because of this bug.

The solution is to conservatively pass `SCEV::FlagAnyWrap` which is always a valid thing to do.

Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D49471

llvm-svn: 337435
2018-07-19 01:46:21 +00:00
Peter Collingbourne
7f3dd14a90 Rename __asan_gen_* symbols to ___asan_gen_*.
This prevents gold from printing a warning when trying to export
these symbols via the asan dynamic list after ThinLTO promotes them
from private symbols to external symbols with hidden visibility.

Differential Revision: https://reviews.llvm.org/D49498

llvm-svn: 337428
2018-07-18 22:23:14 +00:00
Heejin Ahn
417fb38f7f [WebAssembly] Add missing -mattr=+exception-handling guards
Summary:
The use of exception handling instructions should only be enabled with
`-mattr=+exception-handling` option.

Reviewers: jgravelle-google

Subscribers: dschuff, sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D49391

llvm-svn: 337425
2018-07-18 21:42:22 +00:00
Tim Northover
af54b151ba Revert "ARM: switch armv7em triple to hard-float defaults and libcalls."
This reverts commit r337385 until it can be targeted at MachO only.

llvm-svn: 337424
2018-07-18 21:32:49 +00:00
David Blaikie
21f2c46490 Fix some tests that had (implied) duplicate mtriple
I 'fixed' one of these to use %llc_dwarf unnecessarily, so switch them
both back to using llc directly.

llvm-svn: 337423
2018-07-18 20:37:01 +00:00
Simon Pilgrim
bba5fdec33 [X86][SSE] Canonicalize scalar fp arithmetic shuffle patterns
As discussed on PR38197, this canonicalizes MOVS*(N0, OP(N0, N1)) --> MOVS*(N0, SCALAR_TO_VECTOR(OP(N0[0], N1[0])))

This returns the scalar-fp codegen lost by rL336971.

Additionally it handles the OP(N1, N0)) case for commutable (FADD/FMUL) ops.

Differential Revision: https://reviews.llvm.org/D49474

llvm-svn: 337419
2018-07-18 19:55:19 +00:00
Xin Tong
1664030ee9 Skip debuginfo intrinsic in markLiveBlocks.
Summary:
The optimizer is 10%+ slower with vs without debuginfo. I started checking where
the difference is coming from.

I compiled sqlite3.c with and without debug info from CTMark and compare the time difference.

I use Xcode Instrument to find where time is spent. This brings about 20ms, out of ~20s.

Reviewers: davide, hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, aprantl, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D49337

llvm-svn: 337416
2018-07-18 18:40:45 +00:00
Roman Lebedev
99b7f809a2 Add (very partial) Kate syntax highlighting definition for TableGen
This is very clearly not very good, and is very partial.
But this is better than nothing at all, and shouldn't
hurt those who don't need it.

If there are others interested in this functionality,
it will be great to further improve this.

{F6253091}

Reviewed By: Bigcheese

Differential Revision: https://reviews.llvm.org/D47080

llvm-svn: 337415
2018-07-18 18:35:27 +00:00
Nirav Dave
39299dcb1a [DAG] Add testcase.
llvm-svn: 337414
2018-07-18 18:34:52 +00:00
David Blaikie
22f478a1ba [DebugInfo] Dwarfv5: Avoid unnecessary base_address specifiers in rnglists
Since DWARFv5 rnglists are self descriptive and have distinct encodings
for base-relative (offset_pair) and absolute (start_length) entries,
there's no need to use a base address specifier when describing a lone
address range in a section.

Use that, and improve the test coverage a bit here to include cases like
this and others.

llvm-svn: 337411
2018-07-18 18:04:42 +00:00
Nirav Dave
c2ecd4b259 [ScheduleDAG] Fix unfolding of SUnits to already existent nodes.
Summary:
If unfolding an SUnit results in both load or the operation using it which
already exist in the DAG, abort the unfold if they are already scheduled.
If not, make sure we don't add duplicate dependencies.

This fixes PR37916.

Reviewers: davide, eli.friedman, fhahn, bogner

Subscribers: MatzeB, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D48666

llvm-svn: 337409
2018-07-18 18:01:03 +00:00
Paul Semel
e4ae3a86ed [llvm-readobj] Generic -string-dump option
Differential Revision: https://reviews.llvm.org/D49470

llvm-svn: 337408
2018-07-18 18:00:41 +00:00
Teresa Johnson
0c3cec6697 [docs] Update GoldPlugin documentation
Summary:
Updated and reorganized. Made the following additions:
1) How to see if ld.gold is installed, and whether it is the current
default.
2) How to install ld.gold as the default or alternatively use
-fuse-ld=gold.
3) Move the part about installing the newly built ld-new as the default
to the prior section and how to use --enable-gold=default to do it
automatically on install.
4) Add a note about ld.bfd supporting plugins but indicate that it is
not tested by the LLVM project and gold is the recommended linker for
use with the gold plugin.

Fixes PR32760.

Reviewers: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D49490

llvm-svn: 337404
2018-07-18 17:10:17 +00:00
Wei Mi
a7c377ee73 [RegAlloc][NFC] Fix the help string of the option "huge-size-for-split".
llvm-svn: 337402
2018-07-18 16:56:33 +00:00
Paul Semel
d8d82c148d [llvm-objdump] Add -demangle (-C) option
Differential Revision: https://reviews.llvm.org/D49043

llvm-svn: 337401
2018-07-18 16:39:21 +00:00
Roman Lebedev
7bac7e0d2e [NFC][X86][AArch64][DAGCombine] More tests for optimizeSetCCOfSignedTruncationCheck()
At least one of these cases is more canonical,
so we really do have to handle it.
https://godbolt.org/g/pkzP3X
https://rise4fun.com/Alive/pQyh

llvm-svn: 337400
2018-07-18 16:19:06 +00:00
Benjamin Kramer
3a2da5387f [llvm-objcopy] %python wants to be in quotes, because it might contain spaces
llvm-svn: 337399
2018-07-18 16:17:53 +00:00
Nirav Dave
e1c8051ab6 [MC] Fix nested macro body parsing
Add missing .rep case in nestlevel checking for macro body parsing.

llvm-svn: 337398
2018-07-18 16:17:03 +00:00
Simon Atanasyan
b00c7cab3e [mips] Fix predicate for the MipsTruncIntFP pattern
This is a follow-up to the rL337171. This patch fixes regression
introduced by the r337171 and enables MipsTruncIntFP pattern.

Differential revision: https://reviews.llvm.org/D49469

llvm-svn: 337392
2018-07-18 14:11:22 +00:00
Chandler Carruth
07cf7f21e0 [x86/SLH] Add the design document for Speculative Load Hardening,
a Spectre v1 mitigation.

This was initially posted w/ the patch implementing this, got some basic
review there. Also, it is generated from a the Google doc that I shared
as part of the Speculative Load Hardening RFC and which has seen pretty
widespread review at this point.

However, as the patches are landing in LLVM, I wanted to land the docs
as well. But it seemed like a bad idea to have them in the same commit
in case of reverts or other things. So the docs are split out here.

Thanks for all the review so far, and further review and improvements to
the documentation here welcome. Please feel free to keep hammering on
the code review or Google document.

Note that this is a markdown document which Sphinx doesn't yet process.
But we can add support for that after and this should get picked up
(and I'm preparing patches for that). Also, this gets the document
itself into a nice shared place where we can iterate on it.

Differential Revision: https://reviews.llvm.org/D49433

llvm-svn: 337391
2018-07-18 14:05:14 +00:00
Simon Pilgrim
0e1947ac6c [SLPVectorizer] Avoid duplicate scalar cost calculations in BoUpSLP::getEntryCost. NFCI.
Pulled out from D49225, we have a lot of repeated scalar cost calculations, often with arguments that don't look the same but turn out to be.

llvm-svn: 337390
2018-07-18 13:53:55 +00:00
Tim Northover
86f6d37bb3 [Support] Build fix for Haiku when checking for a local filesystem
Haiku does not expose information about local versus remote mounts, so just
return false, like Cygwin.

Patch by Niels Sascha Reedijk.

llvm-svn: 337389
2018-07-18 13:42:18 +00:00
Simon Pilgrim
6c4c2eada8 [X86][SSE] Remove BLENDPD canonicalization from combineTargetShuffle
When rL336971 removed the scalar-fp isel patterns, we lost the need for this canonicalization - commutation/folding can handle everything else.

llvm-svn: 337387
2018-07-18 13:01:20 +00:00
Tim Northover
bdb84fa41e ARM: stop explicitly marking armv7k libcalls as hard-float. NFC.
Since the triple's default is hard float, the libcalls will already use VFP
registers.

llvm-svn: 337386
2018-07-18 12:37:43 +00:00
Tim Northover
68b603dfcd ARM: switch armv7em triple to hard-float defaults and libcalls.
We were emitting incorrect calls to libm functions that LLVM had decided it
knew about because the default is soft-float.

llvm-svn: 337385
2018-07-18 12:37:04 +00:00
Tim Northover
77e1f48b87 ARM: deduplicate hard-float detection code. NFC.
ARMSubtarget had a copy/pasted block to determine whether the target was
hard-float, but it just delegated to triple features anyway so it's better at
the TargetMachine level.

llvm-svn: 337384
2018-07-18 12:36:25 +00:00
Sander de Smalen
670e3761c2 [AArch64][SVE] Asm: Support for unpredicated FP operations.
This patch adds support for the following unpredicated
floating-point instructions:

  FADD      Floating point add
  FSUB      Floating point subtract
  FMUL      Floating point multiplication
  FTSMUL    Floating point trigonometric starting value
  FRECPS    Floating point reciprocal step
  FRSQRTS   Floating point reciprocal square root step

The instructions have the following assembly format:
  fadd z0.h, z1.h, z2.h
and have variants for 16, 32 and 64-bit FP elements.

llvm-svn: 337383
2018-07-18 11:59:12 +00:00
Andrea Di Biagio
667da2dc91 [TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.
This should have been part of r337378. I forgot to svn add it before committing
the change.

llvm-svn: 337380
2018-07-18 11:16:31 +00:00
Max Kazantsev
29fa9d81d4 [NFC] Make a test more neat
llvm-svn: 337379
2018-07-18 11:03:40 +00:00
Andrea Di Biagio
ef7e76afcf [Tablegen][PredicateExpander] Add the ability to define checks for invalid registers.
This was discussed in review D49436.

llvm-svn: 337378
2018-07-18 11:03:22 +00:00
Roman Lebedev
01cf565658 [InstCombine] Re-commit: Fold 'check for [no] signed truncation' pattern
Summary:
[[ https://bugs.llvm.org/show_bug.cgi?id=38149 | PR38149 ]]

As discussed in https://reviews.llvm.org/D49179#1158957 and later,
the IR for 'check for [no] signed truncation' pattern can be improved:
https://rise4fun.com/Alive/gBf
^ that pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958 https://bugs.llvm.org/show_bug.cgi?id=21530
in signed case, therefore it is probably a good idea to improve it.

The DAGCombine will reverse this transform, see
https://reviews.llvm.org/D49266

This transform is surprisingly frustrating.
This does not deal with non-splat shift amounts, or with undef shift amounts.
I've outlined what i think the solution should be:
```
  // Potential handling of non-splats: for each element:
  //  * if both are undef, replace with constant 0.
  //    Because (1<<0) is OK and is 1, and ((1<<0)>>1) is also OK and is 0.
  //  * if both are not undef, and are different, bailout.
  //  * else, only one is undef, then pick the non-undef one.
```

This is a re-commit, as the original patch, committed in rL337190
was reverted in rL337344 as it broke chromium build:
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
Proofs that the fixed folds are ok: https://rise4fun.com/Alive/VYM

Differential Revision: https://reviews.llvm.org/D49320

llvm-svn: 337376
2018-07-18 10:55:17 +00:00
Simon Pilgrim
8b05ab197f [X86][SSE] Add extra scalar fop + blend tests for commuted inputs
While working on PR38197, I noticed that we don't make use of FADD/FMUL being able to commute the inputs to support the addps+movss -> addss style combine

llvm-svn: 337375
2018-07-18 10:54:13 +00:00
Daniel Cederman
719f1fd19c Revert "[Sparc] Use the IntPair reg class for r constraints with value type f64"
This reverts commit 55222c9183c6e07f53a54c4061677734f54feac1.

I missed that this patch has a dependency on https://reviews.llvm.org/D49219
that has not been approved yet.

llvm-svn: 337373
2018-07-18 10:05:30 +00:00
Sander de Smalen
3ce570ffaa [AArch64][SVE] Asm: Support for UDOT/SDOT instructions.
The signed/unsigned DOT instructions perform a dot-product on
quadtuplets from two source vectors and accumulate the result in
the destination register. The instructions come in two forms:

Vector form, e.g.
  sdot  z0.s, z1.b, z2.b     - signed dot product on four 8-bit quad-tuplets,
                               accumulating results in 32-bit elements.

  udot  z0.d, z1.h, z2.h     - unsigned dot product on four 16-bit quad-tuplets,
                               accumulating results in 64-bit elements.

Indexed form, e.g.
  sdot  z0.s, z1.b, z2.b[3]  - signed dot product on four 8-bit quad-tuplets
                               with specified quadtuplet from second
                               source vector, accumulating results in 32-bit
                               elements.
  udot  z0.d, z1.h, z2.h[1]  - dot product on four 16-bit quad-tuplets
                               with specified quadtuplet from second
                               source vector, accumulating results in 64-bit
                               elements.

llvm-svn: 337372
2018-07-18 09:37:51 +00:00
George Rimar
863e12ad16 [llvm-objdump] - An attempt to fix BB after r337361.
Seems r337361 is the reason of the following ARM BB failures:
http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick
http://lab.llvm.org:8011/builders/clang-cmake-armv8-full/builds/4633

Reason is unclear to me, other bots are OK.
If this will not help, I'll revert r337361.

llvm-svn: 337371
2018-07-18 09:25:36 +00:00
Daniel Cederman
1b9c505cfe [Sparc] Use the IntPair reg class for r constraints with value type f64
Summary: This is how it appears to be handled in GCC and it prevents a
"Unknown mismatch" error in the SelectionDAGBuilder.

Reviewers: venkatra, jyknight, jrtc27

Reviewed By: jyknight, jrtc27

Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D49218

llvm-svn: 337370
2018-07-18 09:25:33 +00:00
Sander de Smalen
ea0a070f6a [AArch64][SVE] Asm: Integer divide instructions.
This patch adds the following predicated instructions:

  UDIV    Unsigned divide active elements
  UDIVR   Unsigned divide active elements, reverse form.
  SDIV    Signed divide active elements
  SDIVR   Signed divide active elements, reverse form.

e.g.
  udiv  z0.s, p0/m, z0.s, z1.s
    (unsigned divide active elements in z0 by z1, store result in z0)

  sdivr z0.s, p0/m, z0.s, z1.s
    (signed divide active elements in z1 by z0, store result in z0)

llvm-svn: 337369
2018-07-18 09:17:29 +00:00
Simon Pilgrim
0bf968b56a Fix -Wdocumentation warning. NFCI.
llvm-svn: 337368
2018-07-18 09:10:18 +00:00
Simon Pilgrim
77027a4de0 Fix -Wdocumentation warning. NFCI.
llvm-svn: 337367
2018-07-18 09:07:54 +00:00
Philip Pfaffe
1002ce3706 [CMake] Export the LLVM_LINK_LLVM_DYLIB setting
Summary:
When building out-of-tree tools, there are several macros available to
automate linking against llvm. An examples is `add_llvm_executable`, or
the clang variant of this.

These macros use the LLVM_LINK_LLVM_DYLIB option to decide whether to
link against libraries defined by setting LLVM_LINK_COMPONENTS or to
link against libLLVM instead. Currently this is problematic in
out-of-tree targets, because they cannot identify whether this option is
required or even available. If the option was enabled in LLVM's own
build, the clang libraries are built against libLLVM, so a client
linking against those must link against it too. On the other hand the
client can't just always link against it, because it might not be
available.

This is related to D44391, but that change assumed the client knew
whether they wanted the dylib or not.

Reviewers: mgorny, beanz, labath

Reviewed By: mgorny

Subscribers: bollu, llvm-commits

Differential Revision: https://reviews.llvm.org/D49193

llvm-svn: 337366
2018-07-18 08:53:31 +00:00
Roman Lebedev
ba38e8c25f [NFC][InstCombine] i65 tests for 'check for [no] signed truncation' pattern
Those initially broke chromium build:
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832

llvm-svn: 337364
2018-07-18 08:49:51 +00:00
George Rimar
98853328e2 [llvm-objdump] - Stop reporting bogus section IDs.
Imagine we have a file with few sections, and one of them is .foo
with index N != 0.

Problem is that when llvm-objdump is given a -section=.foo parameter
it lists .foo as a section at index 0. That makes impossible to write
test cases which needs to find the index of the particular section,
while ignoring dumping of others.

The patch fixes that.

Differential revision: https://reviews.llvm.org/D49372

llvm-svn: 337361
2018-07-18 08:34:35 +00:00
George Rimar
691d967bcc [llvm-readobj] - Teach tool to dump objects with >= SHN_LORESERVE of sections.
http://www.sco.com/developers/gabi/2003-12-17/ch4.eheader.html

says that e_shnum and/or e_shstrndx may have special values if
"the number of sections is greater than or equal to SHN_LORESERVE" or
"the section name string table section index is greater than or equal to SHN_LORESERVE (0xff00)"

Previously llvm-readobj was unable to dump such files, patch changes that.

I had to add a precompiled test case because it does not seem possible to
prepare a test using yaml2obj or llvm-mc (not clear how to make .shstrtab
to have index >= SHN_LORESERVE).

Differential revision: https://reviews.llvm.org/D49369

llvm-svn: 337360
2018-07-18 08:19:58 +00:00
Roman Lebedev
6ac8af1030 Revert test changes part of "Revert "[InstCombine] Fold 'check for [no] signed truncation' pattern""
We want the test to remain good anyway.
I think the fix is incoming.

This reverts part of commit rL337344.

llvm-svn: 337359
2018-07-18 08:15:13 +00:00
Sander de Smalen
c457534655 [AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
  MUL   - multiply vectors, e.g.
    mul z0.h, p0/m, z0.h, z1.h
        - multiply with immediate, e.g.
    mul z0.h, z0.h, #127

  SMULH - signed multiply returning high half, e.g.
    smulh z0.h, p0/m, z0.h, z1.h

  UMULH - unsigned multiply returning high half, e.g.
    umulh z0.h, p0/m, z0.h, z1.h

llvm-svn: 337358
2018-07-18 08:10:03 +00:00
Craig Topper
048d1aa2e7 [X86] Enable commuting of VUNPCKHPD to VMOVLHPS to enable load folding by using VMOVLPS with a modified address.
This required an annoying amount of tablegen multiclass changes to make only VUNPCKHPDZ128rr commutable.

llvm-svn: 337357
2018-07-18 07:31:32 +00:00
Craig Topper
4a86b975b4 [X86] Add test case for missed opportunity to commute vunpckhpd to enable use of vmovlps to fold a load.
We do this transform for SSE, but not AVX or AVX512VL.

llvm-svn: 337356
2018-07-18 07:31:30 +00:00
Craig Topper
e74ff94e87 [X86] Regenerate fma.ll checks using current version of the script which produces different regular expressions on spills and reloads. NFC
llvm-svn: 337354
2018-07-18 07:08:28 +00:00