RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-22 11:55:12 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
63,337 Commits 4 Branches 5 Tags
Commit Graph

40543 Commits

Author SHA1 Message Date
Evan Cheng
4929ba9d20 ArchV7M implies HW division instructions. 
llvm-svn: 110797
 2010-08-11 07:00:16 +00:00
Evan Cheng
31e15214c6 ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
llvm-svn: 110796
 2010-08-11 06:57:53 +00:00
Evan Cheng
273160895e Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Daniel Dunbar
bc7c0a60da MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
llvm-svn: 110794
 2010-08-11 06:37:20 +00:00
Daniel Dunbar
63628f1443 MC/ARM: Split mnemonic on '.' characters. 
llvm-svn: 110793
 2010-08-11 06:37:16 +00:00
Daniel Dunbar
bbaa88a848 MC/ARM: Fill in ARMOperand::dump a bit. 
llvm-svn: 110792
 2010-08-11 06:37:12 +00:00
Daniel Dunbar
4882ffc373 llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching. 
llvm-svn: 110791
 2010-08-11 06:37:09 +00:00
Daniel Dunbar
ee80a239ed MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
llvm-svn: 110790
 2010-08-11 06:37:04 +00:00
Daniel Dunbar
74ed9321a3 MC/ARM: Add an ARMOperand class for condition codes. 
llvm-svn: 110788
 2010-08-11 06:36:53 +00:00
Evan Cheng
e67c4c3723 Really control isel of barrier instructions with cpu feature. 
llvm-svn: 110787
 2010-08-11 06:36:31 +00:00
Evan Cheng
e5bab36c75 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786
 2010-08-11 06:30:38 +00:00
Evan Cheng
5fca4ca5f9 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
 2010-08-11 06:22:01 +00:00
Daniel Dunbar
89a64ee590 MC/ARM: Switch to using the generated match functions instead of stub implementations. 
llvm-svn: 110783
 2010-08-11 05:24:50 +00:00
Daniel Dunbar
0d725e0080 MC/ARM: Enable generation of the ARM asm matcher, not that it can do much. 
llvm-svn: 110782
 2010-08-11 05:09:20 +00:00
Daniel Dunbar
8311cf950b ARM: Mark some disassembler only instructions as not available for matching -- 
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781
 2010-08-11 04:46:13 +00:00
Daniel Dunbar
a77e3fc8d8 ARM: Quote $p in an asm string. 
llvm-svn: 110780
 2010-08-11 04:46:10 +00:00
Owen Anderson
0692635e68 Improve indentation. 
llvm-svn: 110778
 2010-08-11 04:24:25 +00:00
Bill Wendling
615aad17f7 Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds. 
llvm-svn: 110762
 2010-08-11 00:23:00 +00:00
Bill Wendling
735305d4d8 Mark ARM compare instructions as isCompare. 
llvm-svn: 110761
 2010-08-11 00:22:27 +00:00
Dan Gohman
603e66618f When analyzing loop exit conditions combined with and and or, don't 
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758
 2010-08-11 00:12:36 +00:00
Bob Wilson
0650cceb38 Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
 2010-08-11 00:01:18 +00:00
Dan Gohman
7e49302e9a Rename and reorder the arguments to isImpliedCond, for consistency and clarity. 
llvm-svn: 110750
 2010-08-10 23:46:30 +00:00
Evan Cheng
966ed540a6 CBZ and CBNZ are implemented. 
llvm-svn: 110745
 2010-08-10 23:27:11 +00:00
Bruno Cardoso Lopes
6eb24fd744 Add AVX matching patterns to Packed Bit Test intrinsics. 
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744
 2010-08-10 23:25:42 +00:00
Owen Anderson
a095d3fe73 Now that we're using ConstantRange to represent potential values, make use of that represenation to 
create constraints from comparisons other than eq/neq.

llvm-svn: 110742
 2010-08-10 23:20:01 +00:00
Nate Begeman
713062e756 Add the minimal amount of smarts necessary to instcombine of shufflevectors to recognize 
patterns generated by clang for transpose of a matrix in generic vectors.  This is made
of two parts:

1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.

Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.

llvm-svn: 110734
 2010-08-10 21:38:12 +00:00
Bill Wendling
c8117e507d Turn optimize compares back on with fix. We needed to test that a machine op was 
a register before checking if it was defined.

llvm-svn: 110733
 2010-08-10 21:38:11 +00:00
Jakob Stoklund Olesen
e0262a6e24 Give up on register class recalculation when the register is used with subreg 
operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".

llvm-svn: 110730
 2010-08-10 21:16:16 +00:00
Dan Gohman
9abea56ce4 Revert r110718; it broke clang-i386-darwin9. 
llvm-svn: 110726
 2010-08-10 20:49:33 +00:00
Jakob Stoklund Olesen
6036d58c40 Avoid editing the current live interval during remat. 
The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.

llvm-svn: 110721
 2010-08-10 20:45:07 +00:00
Jakob Stoklund Olesen
d3f939d7a2 More debug spew 
llvm-svn: 110720
 2010-08-10 20:45:01 +00:00
Bill Wendling
0acc8f8a02 Turn optimize cmps on by default so that we can get some testing by the nightly 
ARM testers.

llvm-svn: 110718
 2010-08-10 20:23:02 +00:00
Devang Patel
17606414a4 Add missing argument. CreateCompositeTypeEx() users, please verify. 
llvm-svn: 110717
 2010-08-10 20:22:49 +00:00
Owen Anderson
a3a2b79f01 Switch over to using ConstantRange to track integral values. 
llvm-svn: 110714
 2010-08-10 20:03:09 +00:00
Devang Patel
9b12559c4f Do not forget debug info for enums. Use named mdnode to keep track of these types. 
llvm-svn: 110712
 2010-08-10 20:01:20 +00:00
Evan Cheng
784a286b92 Delete some unused instructions. 
llvm-svn: 110710
 2010-08-10 19:36:22 +00:00
Evan Cheng
d9a1b0d046 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object. 
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.

llvm-svn: 110707
 2010-08-10 19:30:19 +00:00
Jakob Stoklund Olesen
245a1faf76 Implement register class inflation. 
When splitting a live range, the new registers have fewer uses and the
permissible register class may be less constrained. Recompute the register class
constraint from the uses of new registers created for a split. This may let them
be allocated from a larger set, possibly avoiding a spill.

llvm-svn: 110703
 2010-08-10 18:37:40 +00:00
Daniel Dunbar
872e84afb5 Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP 
register is", it breaks a couple test-suite tests.

llvm-svn: 110701
 2010-08-10 18:32:02 +00:00
Daniel Dunbar
f7233103ff MC/AsmParser: Fix a bug in macro argument parsing, which was dropping 
parentheses from argument lists.

llvm-svn: 110692
 2010-08-10 17:38:52 +00:00
Jakob Stoklund Olesen
e51a747336 Recalculate the spill weight and allocation hint for virtual registers created 
during live range splitting.

llvm-svn: 110686
 2010-08-10 17:07:22 +00:00
Michael J. Spencer
26a45fe57e Revert "MC/MachO: Fix possible null pointer dereference." 
This reverts commit 110575.

Target.isAbsolute() is true if SD would be null.

llvm-svn: 110683
 2010-08-10 16:00:49 +00:00
Chandler Carruth
69dd8d673c Mark this variable as used. 
llvm-svn: 110667
 2010-08-10 10:39:25 +00:00
Tobias Grosser
7b96737b7f RegionInfo: Do not assert if a BB is not part of the dominance tree. 
llvm-svn: 110665
 2010-08-10 09:54:35 +00:00
Devang Patel
84f48b5483 Handle TAG_constant for integers. 
llvm-svn: 110656
 2010-08-10 07:11:13 +00:00
Evan Cheng
3d47dbe761 Fix ARM hasFP() semantics. It should return true whenever FP register is 
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.

llvm-svn: 110655
 2010-08-10 06:26:49 +00:00
Bill Wendling
eb1b0564a7 Update CMake...sorry for the breakage. 
llvm-svn: 110654
 2010-08-10 05:16:06 +00:00
Devang Patel
8edc7575a4 Simplify. 
llvm-svn: 110653
 2010-08-10 04:12:17 +00:00
Devang Patel
191ed4c41d Drop "const". It does not add value here. 
llvm-svn: 110652
 2010-08-10 04:09:06 +00:00
Bruno Cardoso Lopes
f1928b60c0 Add AVX movnt{pd,ps,dq} 256-bit intrinsics 
llvm-svn: 110650
 2010-08-10 02:49:24 +00:00