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442 Commits

Author SHA1 Message Date
Evan Cheng
37d647c562 Add a FIXME comment. 
llvm-svn: 25635
 2006-01-26 02:13:31 +00:00
Evan Cheng
849d522805 Incoming (and optional) flag bugs. They may be embedded inside a inner node of 
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.

llvm-svn: 25627
 2006-01-26 00:22:25 +00:00
Evan Cheng
dd2ee4821a Fix an optional in flag bug. 
llvm-svn: 25590
 2006-01-24 20:46:50 +00:00
Evan Cheng
1f68845c8c Optional InFlag was not being included in node. 
llvm-svn: 25588
 2006-01-24 20:07:38 +00:00
Evan Cheng
d3713a9b9a Prevent folding of a node with multiple uses if the node already folds a load! 
Here is an example where the load ended up being done twice:

%A = global uint 0

uint %test(uint %B, ubyte %C) {
	%tmp = load uint *%A;
	%X = shl uint %tmp, ubyte %C
	%Cv = sub ubyte 32, %C
	%Y = shr uint %B, ubyte %Cv
	%Z = or uint %Y, %X
	store uint %Z, uint* %A
	ret uint %Z
}

==>

	subl $4, %esp
	movl %ebx, (%esp)
	movl 8(%esp), %edx
	movl A, %eax
	movb 12(%esp), %bl
	movb %bl, %cl
	shldl %cl, %edx, %eax
	movb %bl, %cl
	shldl %cl, %edx, A
	movl (%esp), %ebx
	addl $4, %esp
	ret

llvm-svn: 25471
 2006-01-20 01:11:03 +00:00
Evan Cheng
4a3ee9d5a6 Bug fix. Flag operand number may be calculated incorrectly. 
llvm-svn: 25465
 2006-01-19 21:57:10 +00:00
Evan Cheng
f168c680e5 Use pattern information to determine whether the use expects this 
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.

llvm-svn: 25458
 2006-01-19 10:12:58 +00:00
Evan Cheng
49fa8f2cea Prevent unnecessary CopyToReg when the same HW register appears in two spots 
in the pattern.

llvm-svn: 25437
 2006-01-19 01:55:45 +00:00
Chris Lattner
6efb726290 fix a broken comment 
llvm-svn: 25411
 2006-01-17 21:31:18 +00:00
John Criswell
ab12f83120 Regenerated the Lex and Yacc output files on Linux. It seems that our 
Linux machines don't like the source code generated on MacOS X for some
reason.

llvm-svn: 25394
 2006-01-17 17:01:34 +00:00
Evan Cheng
e840301269 Emit a type matching check for ComplexPatterns. 
llvm-svn: 25392
 2006-01-17 07:36:41 +00:00
Evan Cheng
ddc62a9b61 Type inferencing bug 
llvm-svn: 25337
 2006-01-15 10:04:45 +00:00
Evan Cheng
dc7ec6c63e Allow transformation from GlobalAddress to TargetGlobalAddress and 
ExternalSymbol to TargetExternalSymbol.

llvm-svn: 25252
 2006-01-12 19:35:54 +00:00
Evan Cheng
bbe910088d GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol 
llvm-svn: 25245
 2006-01-12 07:54:57 +00:00
Evan Cheng
5fa1397b29 Some minor fixes. 
llvm-svn: 25227
 2006-01-11 22:16:13 +00:00
Chris Lattner
4e465047c1 Always select target registers to themselves 
llvm-svn: 25218
 2006-01-11 19:52:27 +00:00
Chris Lattner
0343518492 Emit an error instead of an assertion if trying to do bogus things in result patterns. 
llvm-svn: 25194
 2006-01-11 01:33:49 +00:00
Robert Bocchino
9a57550e4e Added support for the extractelement operation. 
llvm-svn: 25181
 2006-01-10 19:05:34 +00:00
Evan Cheng
7b8f8c317e * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and 
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.

llvm-svn: 25154
 2006-01-09 18:27:06 +00:00
Evan Cheng
353958d60c Pattern complexity calculation fix. 
llvm-svn: 25133
 2006-01-06 22:19:44 +00:00
Evan Cheng
1d376c6eb2 Tweak pattern complexity calc. 
llvm-svn: 25122
 2006-01-06 02:30:23 +00:00
Evan Cheng
c6ad7a02a8 Bug fix wrt chain operand. 
llvm-svn: 25115
 2006-01-06 00:41:12 +00:00
Jeff Cohen
2230844c7b Replace fix with one less disruptive to the original code. 
Also note that GCC 4.1 also correctly flags the syntax error.

llvm-svn: 25076
 2006-01-04 03:23:30 +00:00
Jeff Cohen
8c5173a440 Tblgen was generating syntactically illegal C++ code like: 
SDOperand Tmp0,Tmp1,Tmp2,Tmp3,;

GCC has a bug (24907) in which is fails to catch this, but VC++ correctly
notes its illegality, so tblgen must be taught to only generate legal C++.

llvm-svn: 25075
 2006-01-04 03:15:19 +00:00
Chris Lattner
5a6761490a Remove obsolete comment, make things look a bit nicer 
llvm-svn: 25070
 2006-01-04 00:32:01 +00:00
Chris Lattner
ae035f3604 reduce stack usage of the recursive SelectCode function by out-lining each 
case of the switch statement into its own method.

llvm-svn: 25069
 2006-01-04 00:25:00 +00:00
Chris Lattner
f6418363ba Remove my previous ugly hack that tries to reduce the stack space usage 
of SelectCode to make way for a better solution.

llvm-svn: 25068
 2006-01-03 22:55:16 +00:00
Duraid Madina
d3cf232a4f HP-UX DVDs are crunchy and good to eat 
llvm-svn: 25052
 2005-12-30 16:41:48 +00:00
Duraid Madina
c4a1bfd13d almost got the HP-UX tester up.. :) 
llvm-svn: 25051
 2005-12-30 14:56:37 +00:00
Nate Begeman
ec7c28a28c Add support for generating v4i32 altivec code 
llvm-svn: 25046
 2005-12-30 00:12:56 +00:00
Duraid Madina
d63b3a13cc This gets most of the backends building with HP HappyC++. 
llvm-svn: 25029
 2005-12-27 10:56:22 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Duraid Madina
b8be651393 more standards-compliance stuff 
llvm-svn: 25014
 2005-12-26 05:08:55 +00:00
Andrew Lenharth
b42cc57048 support targetexternalsym 
llvm-svn: 25005
 2005-12-24 23:36:59 +00:00
Evan Cheng
bd79f871a2 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG 
support which is fragile.
* Fixed a number of bugs.

llvm-svn: 24996
 2005-12-23 22:11:47 +00:00
Chris Lattner
d752db6276 silence some bogus gcc warnings 
llvm-svn: 24962
 2005-12-22 20:37:36 +00:00
Evan Cheng
b18b8c847f Attempt to fix a crash on WIN32. 
llvm-svn: 24936
 2005-12-22 02:35:21 +00:00
Evan Cheng
578fad3f9d * Added support for FLAG - a special nameless flag register. Can be used as 
either an operand or a result.
* Fixed some more flag / chain bugs.

llvm-svn: 24933
 2005-12-22 02:24:50 +00:00
Evan Cheng
3b09247bb9 Allows instructions which no explicit operands. e.g. X86 RET which has but 
an implicit flag operand.

llvm-svn: 24916
 2005-12-21 20:20:49 +00:00
Chris Lattner
643e6c2b9e Eliminate some GCC warnings from the generated code 
llvm-svn: 24897
 2005-12-21 05:31:05 +00:00
Evan Cheng
4106feae54 Fix the semantic of Requires<[cond]> to mean if (!cond) goto PXXFail; 
llvm-svn: 24883
 2005-12-20 20:08:01 +00:00
Chris Lattner
28cf136707 This ugly patch works around a GCC bug where it is compiling SelectCode to 
use too much stack space, overflowing the stack for large functions.  Instead
of emitting new SDOperands in each match block, we emit some common ones at
the top of SelectCode then reuse them when possible.

This reduces the stack size of SelectCode from 28K to 21K.  Note that GCC
compiles it to 512 bytes :-/

I've filed GCC PR 25505 to track this.

llvm-svn: 24882
 2005-12-20 19:41:03 +00:00
Evan Cheng
98c6b52236 Now support instructions with implicit write to non-flag registers. 
llvm-svn: 24878
 2005-12-20 07:37:41 +00:00
Evan Cheng
63d897b0e2 Lefted out a fix in the previous check in. 
llvm-svn: 24873
 2005-12-20 00:06:17 +00:00
Evan Cheng
e93635d0ac Fix another bug related to chain / flag. 
llvm-svn: 24868
 2005-12-19 22:40:04 +00:00
Evan Cheng
c56f9824db Fixes for a number of bugs: save flag results in CodeGenMap, folded chains 
may not all have ResNo == 0.

llvm-svn: 24858
 2005-12-19 07:18:51 +00:00
Chris Lattner
abadc27396 Handle basic block nodes 
llvm-svn: 24833
 2005-12-18 21:05:44 +00:00
Chris Lattner
5dfbcbb8be More fixes for Selection of copyto/fromreg with a flag 
llvm-svn: 24829
 2005-12-18 15:45:51 +00:00
Chris Lattner
5322894560 Select copytoreg and copyfromreg nodes that have flag operands correctly. 
llvm-svn: 24827
 2005-12-18 15:28:25 +00:00
Evan Cheng
54695fd38d Support for read / write from explicit registers with FlagVT type. 
llvm-svn: 24753
 2005-12-17 01:19:28 +00:00
Evan Cheng
297c23d2e7 Added support to specify predicates. 
llvm-svn: 24715
 2005-12-14 22:02:59 +00:00
Evan Cheng
81f4683257 Skip over srcvalue nodes when generating ISEL code. 
llvm-svn: 24704
 2005-12-14 02:21:57 +00:00
Evan Cheng
518610154b Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ... 
llvm-svn: 24680
 2005-12-12 23:45:21 +00:00
Evan Cheng
1bc6443c22 At top of generated isel SelectCode() is this: 
if (!N.Val->hasOneUse()) {
    std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
    if (CGMI != CodeGenMap.end()) return CGMI->second;
  }

Suppose a DAG like this:

           X
         ^   ^
        /     \
      USE1    USE2

Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!

The fix is to always query CodeGenMap.

llvm-svn: 24679
 2005-12-12 23:22:48 +00:00
Evan Cheng
e7f40a3b8b Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible. 
llvm-svn: 24669
 2005-12-12 19:37:43 +00:00
Nate Begeman
a0e26b25f4 Add support for TargetConstantPool nodes to the dag isel emitter, and use 
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.

llvm-svn: 24657
 2005-12-10 02:36:00 +00:00
Evan Cheng
c8ebe5f6eb Stop emitting a redudant type check for complex pattern node. 
llvm-svn: 24655
 2005-12-10 01:57:33 +00:00
Evan Cheng
8300ae66d1 For instructions which produce no result, e.g. store, chain's Resno == 0. 
llvm-svn: 24652
 2005-12-10 00:09:17 +00:00
Chris Lattner
aaec1f6faa Add a new SDTCisPtrTy constraint, which indicates that an operand must have 
the same type as the pointer type for a target.

llvm-svn: 24649
 2005-12-09 22:57:42 +00:00
Evan Cheng
9586e87904 * Do not allow nodes which produce chain results (e.g. loads) to be folded if 
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
  operand of a chain use.

llvm-svn: 24647
 2005-12-09 22:45:35 +00:00
Evan Cheng
18134d8c96 Prevent folding of instructions which produce chains that have more than 1 real use 
llvm-svn: 24643
 2005-12-09 06:06:08 +00:00
Evan Cheng
1d7435f478 * Make sure complex pattern operands are selected first since their select 
functions can return false and causing the instruction pattern match to fail.
* Code clean up.

llvm-svn: 24642
 2005-12-09 00:48:42 +00:00
Evan Cheng
ed205f20a5 * Added an explicit type field to ComplexPattern. 
* Renamed MatchingNodes to RootNodes.

llvm-svn: 24636
 2005-12-08 02:14:08 +00:00
Evan Cheng
d11d31e0bd Added support for ComplexPattern. These are patterns that require C++ pattern 
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.

llvm-svn: 24634
 2005-12-08 02:00:36 +00:00
Evan Cheng
3d51fa3305 * Infer instruction property hasCtrlDep from pattern if it has one. 
* Fixed a bug related to hasCtrlDep property use.

llvm-svn: 24610
 2005-12-05 23:08:55 +00:00
Chris Lattner
8ef7c0297c Implement PR673: for explicit register references, use type information 
if available

llvm-svn: 24597
 2005-12-05 02:36:37 +00:00
Chris Lattner
e64b6d64d0 Add some methods 
llvm-svn: 24596
 2005-12-05 02:35:08 +00:00
Chris Lattner
5c7d4632f6 Generate code to silence bogus GCC warnings. 
llvm-svn: 24593
 2005-12-05 00:48:51 +00:00
Evan Cheng
cf4f349880 * Commit the fix (by Chris) for a tblgen type inferencing bug. 
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587
 2005-12-04 08:18:16 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Evan Cheng
9c3508e1ab Teach tblgen to accept register source operands in patterns, e.g. 
def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
                 "shl{b} {%cl, $dst|$dst, %CL}",
                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;

This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.

llvm-svn: 24557
 2005-12-01 00:18:45 +00:00
Nate Begeman
b79a074c0a Nuke CodeGenInstruction's ValueType member, it is no longer used. 
llvm-svn: 24556
 2005-12-01 00:12:04 +00:00
Nate Begeman
466eaefd38 Stop checking the ValueType of the CodeGenInstruction. Instead, use the 
ValueType from the RegisterClass or Operands.  This step is necessary to
allow RegisterClasses to have multiple ValueTypes.

llvm-svn: 24555
 2005-12-01 00:06:14 +00:00
Nate Begeman
3935bea6c1 fit into 80 columns 
llvm-svn: 24554
 2005-11-30 23:58:18 +00:00
Chris Lattner
7678189bc6 Make the code generated by tblgen return the result of SelectNodeTo, to 
permit future changes.

llvm-svn: 24553
 2005-11-30 23:08:45 +00:00
Nate Begeman
84be54b731 No longer track value types for asm printer operands, and remove them as 
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
 2005-11-30 18:54:35 +00:00
Nate Begeman
ed43f5159f Fix some copy and paste typos. 
llvm-svn: 24540
 2005-11-30 18:37:14 +00:00
Evan Cheng
5395a80640 Better error message when unrecognized opcode is seen. 
llvm-svn: 24519
 2005-11-29 18:44:58 +00:00
Nate Begeman
e4d7c1b7dd Add the new vector types to tablegen 
llvm-svn: 24514
 2005-11-29 06:19:38 +00:00
Chris Lattner
3727cc7ac0 Initialize this variable on all paths, fixing a crasher in windows. Thanks 
to JeffC for pointing this out.

llvm-svn: 24426
 2005-11-19 07:48:33 +00:00
Chris Lattner
a36ad00a9a Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
 2005-11-19 07:05:57 +00:00
Chris Lattner
6b83dcf750 Validate that the input to 'Pat' patterns is sane. 
llvm-svn: 24393
 2005-11-17 17:43:52 +00:00
Chris Lattner
464f4402cf teach tblgen to be smart enough to handle tglobaladdr nodes 
llvm-svn: 24391
 2005-11-17 07:39:45 +00:00
Chris Lattner
b545ab1ac1 fix a tblgen bug that Evan ran into, where we would lose the '$src' name 
on patterns like "(set R32:$dst, (i32 imm:$src))"

llvm-svn: 24383
 2005-11-16 23:14:54 +00:00
Jim Laskey
42681c1d58 1. Remove ranges from itinerary data. 
2. Tidy up the subtarget emittined code.

llvm-svn: 24172
 2005-11-03 22:47:41 +00:00
Chris Lattner
5a4c453d60 Reject integer literals that are out of range for their type. 
llvm-svn: 24162
 2005-11-03 05:46:11 +00:00
Chris Lattner
e3897f6c24 Add support for immediates directly in the pattern, this allows itanium to 
define:

def : Pat<(i1 1), (CMPEQ r0, r0)>;

llvm-svn: 24149
 2005-11-02 06:49:14 +00:00
Jim Laskey
4cb1e29b27 Allow itineraries to be passed through the Target Machine. 
llvm-svn: 24139
 2005-11-01 20:06:59 +00:00
Jeff Cohen
1a0261fe4f Keep VC++ happy. 
llvm-svn: 24137
 2005-11-01 18:04:06 +00:00
Jim Laskey
1c66d7fb02 Emit itinerary class in instruction info. 
llvm-svn: 24122
 2005-10-31 17:16:46 +00:00
Jim Laskey
d79749c8a5 Generate cpu to itinerary map. 
llvm-svn: 24121
 2005-10-31 17:16:01 +00:00
Chris Lattner
9fd7ba3c84 Make negative immediates in patterns work correctly, silence some warnings 
building the itanium backend.

llvm-svn: 24095
 2005-10-29 16:39:40 +00:00
Chris Lattner
d44a96088b Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :) 
llvm-svn: 24074
 2005-10-28 22:59:53 +00:00
Chris Lattner
06c5e018ef Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately 
reflect what it is.
Convert some more code over to use it.

llvm-svn: 24072
 2005-10-28 22:49:02 +00:00
Chris Lattner
dea00d4a37 Use the new interface Jim added 
llvm-svn: 24071
 2005-10-28 22:43:25 +00:00
Jim Laskey
b86d73937d Removed Mr. Smith from the code. 
llvm-svn: 24070
 2005-10-28 21:47:29 +00:00
Jim Laskey
7bfb35c1ef Added method to return a vector of records for a ListInit of Def field. This 
simplifies using list of records.

llvm-svn: 24069
 2005-10-28 21:46:31 +00:00
Jim Laskey
dba6376b92 Add some commentary. 
llvm-svn: 24055
 2005-10-28 15:20:43 +00:00
Jeff Cohen
744bfe72c0 Keep Visual Studio happy. 
llvm-svn: 24052
 2005-10-28 01:43:09 +00:00
Jim Laskey
1910cbd4dc Now generating instruction itineraries for scheduling. Not my best work, but... 
llvm-svn: 24050
 2005-10-27 19:47:21 +00:00
Jim Laskey
75494b3a8b Simplify. 
llvm-svn: 24015
 2005-10-26 17:49:21 +00:00
Jim Laskey
9ce53d8411 Give full control of subtarget features over to table generated code. 
llvm-svn: 24013
 2005-10-26 17:30:34 +00:00
Chris Lattner
b462de0868 Condcodes are in the ISD namespace 
llvm-svn: 24010
 2005-10-26 17:02:02 +00:00
Chris Lattner
acc8e41a83 Add support for CondCode's 
llvm-svn: 24008
 2005-10-26 16:59:37 +00:00
Chris Lattner
60d02fd01f Emit some boilerplate for targets 
llvm-svn: 23983
 2005-10-25 20:35:14 +00:00
Jim Laskey
bb03da2612 Refactored to make room for more stuff (scheduling info.) 
llvm-svn: 23975
 2005-10-25 15:16:36 +00:00
Chris Lattner
ffa72e8d79 Fix an incompatibility with GCC 4.1, thanks to Vladimir Merzliakov 
for pointing this out!

llvm-svn: 23963
 2005-10-24 15:04:15 +00:00
Chris Lattner
b621e451ba Add the needed #include, emit enums with the sizes of tables, remove 
definitions from the LLVM namespace, since they are all static.

llvm-svn: 23907
 2005-10-23 22:33:08 +00:00
Chris Lattner
fbab2de9dd Remove the obsolete instr selector emitter 
llvm-svn: 23894
 2005-10-23 05:47:52 +00:00
Jim Laskey
f0f90be71c Sort the features and processor lists for the sake of search (and maintainers.) 
llvm-svn: 23879
 2005-10-22 07:59:56 +00:00
Jim Laskey
1fbdee408d Plugin new subtarget backend into the build. 
llvm-svn: 23870
 2005-10-21 19:05:19 +00:00
Jim Laskey
c2e76396fc New TableGen backends for subtarget information. Only command line stuff 
active now.  Scheduling itinerary next.

llvm-svn: 23869
 2005-10-21 19:00:04 +00:00
Chris Lattner
b018f20c7b Make tblgen emit: 
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.

llvm-svn: 23854
 2005-10-21 01:19:59 +00:00
Chris Lattner
1bac5bc8a3 add support for literal immediates in patterns to match, allowing us to 
write things like this:

def : Pat<(add GPRC:$in, 12),
          (ADD12 GPRC:$in)>;

Andrew: if this isn't enough or doesn't work for you, please lemme know.
llvm-svn: 23819
 2005-10-19 04:41:05 +00:00
Chris Lattner
1b8609b570 Add basic support for integer constants in pattern results. 
llvm-svn: 23817
 2005-10-19 04:30:56 +00:00
Chris Lattner
cac2ff4864 Fix some checking that was causing duraid to get a perplexing assertion 
instead of a happy error message

llvm-svn: 23816
 2005-10-19 04:12:14 +00:00
Chris Lattner
39538be7a5 Add support for patterns that have physical registers in them. Testcase: 
def : Pat<(trunc G8RC:$in),
          (OR8To4 G8RC:$in, X0)>;

Even though this doesn't make any sense on PPC :)

llvm-svn: 23815
 2005-10-19 02:07:26 +00:00
Chris Lattner
2a81cf4395 Asserting here is to violent 
llvm-svn: 23814
 2005-10-19 01:55:23 +00:00
Chris Lattner
0816495607 Nate wants to define 'Pat's which turn into instructions that don't have 
patterns.  Certainly a logical request.

llvm-svn: 23810
 2005-10-19 01:27:22 +00:00
Chris Lattner
fbf3838a61 Duraid pointed out that it is impolite to emit PPC:: into the IA64 backend 
llvm-svn: 23780
 2005-10-18 04:41:01 +00:00
Chris Lattner
a4dc9eda40 Make the generated code significantly more memory efficient, by using 
SelectNodeTo instead of getTargetNode when possible.

llvm-svn: 23758
 2005-10-16 01:41:58 +00:00
Chris Lattner
5a4ed7e8ab Implement the last major missing piece in the DAG isel generator: when emitting 
a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction.  This allows FMA32
patterns to not match double expressions for example.

llvm-svn: 23748
 2005-10-15 21:34:21 +00:00
Chris Lattner
3aa7a188b9 Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp 
type constraint.  This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.

llvm-svn: 23730
 2005-10-14 06:25:00 +00:00
Chris Lattner
28621890d9 Fairly serious rework of the typing code to add new int/fp lattice values. 
Overall, no functionality change yet though.

llvm-svn: 23729
 2005-10-14 06:12:03 +00:00
Chris Lattner
c5dbaceaee simplify the code a bit 
llvm-svn: 23728
 2005-10-14 05:08:37 +00:00
Chris Lattner
d83bbd0f14 Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint 
llvm-svn: 23725
 2005-10-14 04:53:53 +00:00
Chris Lattner
81047cdfc0 Implement a couple of new (important) features. 
1. If an operation has to be int or fp and the target only supports one
   int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
   for patterns involving those operators, since we do not emit the code to
   check for them yet.  This prevents PPC from generating FP ops currently.

Also move some code around into more logical places.

llvm-svn: 23724
 2005-10-14 04:11:13 +00:00
Chris Lattner
ee8c8e4562 Do not let getLegalValueTypes return a list with duplicates in it 
llvm-svn: 23723
 2005-10-14 03:54:49 +00:00
Chris Lattner
cccadf388c Emit the value type for each register class. 
llvm-svn: 23584
 2005-10-02 06:23:37 +00:00
Chris Lattner
c744d9398f Rename MRegisterDesc -> TargetRegisterDesc for consistency 
llvm-svn: 23564
 2005-09-30 17:49:27 +00:00
Chris Lattner
f29abb6f4a remove some more initializers 
llvm-svn: 23562
 2005-09-30 17:41:05 +00:00
Chris Lattner
6124aae803 trim down the target info structs now that we have a preferred spill register class for each callee save register 
llvm-svn: 23560
 2005-09-30 17:35:22 +00:00
Chris Lattner
2da37b0d74 Compute a preferred spill register class for each callee-save register 
llvm-svn: 23553
 2005-09-30 06:44:45 +00:00
Chris Lattner
7b69bfc7b6 Fix a warning 
llvm-svn: 23550
 2005-09-30 06:09:50 +00:00
Chris Lattner
7e3972b706 Regenerate 
llvm-svn: 23549
 2005-09-30 04:53:25 +00:00
Chris Lattner
2b7ab1f445 Refactor this a bit to move ParsingTemplateArgs to only apply to classes, 
not defs.

Implement support for forward definitions of classes.  This implements
TableGen/ForwardRef.td.

llvm-svn: 23548
 2005-09-30 04:53:04 +00:00
Chris Lattner
c0830ec129 Regenerate 
llvm-svn: 23546
 2005-09-30 04:42:56 +00:00
Chris Lattner
2e4e3a8678 Generate a parse error instead of a checked exception if template args are 
used on a def.

llvm-svn: 23545
 2005-09-30 04:42:31 +00:00
Chris Lattner
3a8b099f34 regenerate 
llvm-svn: 23543
 2005-09-30 04:11:27 +00:00
Chris Lattner
baa6d77025 Refactor the grammar a bit to implement TableGen/ForwardRef.td 
llvm-svn: 23542
 2005-09-30 04:10:49 +00:00
Chris Lattner
7be456ae2f allow regs to be in multiple reg classes 
llvm-svn: 23540
 2005-09-30 01:33:48 +00:00
Chris Lattner
10a8d57590 Teach tablegen to reassociate operators when possible. This allows it to 
find all of teh pattern matches for EQV from one definition

llvm-svn: 23529
 2005-09-29 22:36:54 +00:00
Chris Lattner
31a9d318a3 Teach tblgen to build permutations of instructions, so that the target author 
doesn't have to specify them manually.  It currently handles associativity,
e.g. knowing that (X*Y)+Z  also matches  X+(Y*Z)  and will be extended in
the future.

It is smart enough to not introduce duplicate patterns or patterns that can
never match.

llvm-svn: 23526
 2005-09-29 19:28:10 +00:00
Chris Lattner
86a339dc34 add support for an associative marker 
llvm-svn: 23502
 2005-09-28 20:58:06 +00:00
Chris Lattner
0231f57a46 Emit an error if instructions or patterns are defined but can never match. 
Currently we check that immediate values live on the RHS of commutative
operators.  Defining ORI like this, for example:

def ORI   : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                    "ori $dst, $src1, $src2",
                    [(set GPRC:$dst, (or immZExt16:$src2, GPRC:$src1))]>;

results in:

tblgen: In ORI: Instruction can never match: Immediate values must be on the RHS of commutative operators!
llvm-svn: 23501
 2005-09-28 19:27:25 +00:00
Chris Lattner
18ccb532b5 collect commutativity information 
llvm-svn: 23499
 2005-09-28 18:28:29 +00:00
Chris Lattner
5dae8ab260 Prefer cheaper patterns to more expensive ones. Print the costs to the generated 
file

llvm-svn: 23492
 2005-09-28 17:57:56 +00:00
Chris Lattner
eeead91a84 Select Constant nodes to TargetConstant nodes 
llvm-svn: 23488
 2005-09-28 16:58:06 +00:00
Chris Lattner
cdeed56e4e memoize the assert results 
llvm-svn: 23457
 2005-09-26 22:10:24 +00:00
Chris Lattner
5c061685a2 Emit the switch stmt cases in alphabetical order instead of pointer order, 
which is not stable.

llvm-svn: 23456
 2005-09-26 21:59:35 +00:00