158224 Commits

Author SHA1 Message Date
Sander de Smalen
61e95dbf6a [AArch64] Asm: Fix parsing of register aliases that have a name starting with 'z'
Summary: This fixes an issue as identified by @rnk in https://reviews.llvm.org/rL321029.

Reviewers: rnk, fhahn, rengolin, efriedma, echristo, olista01

Reviewed By: rnk, fhahn

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, rnk

Differential Revision: https://reviews.llvm.org/D41382

llvm-svn: 321158
2017-12-20 09:45:45 +00:00
Sam Parker
d6872dc64f [AArch64] CCSIDR2 system register
Implement the 'Current Cache Size' register that has been introduced
as part of the Armv8.3 architecture. I originally missed this, and
(hopefully) should be the final patch for assembler support.

Differential Revision: https://reviews.llvm.org/D41396

llvm-svn: 321155
2017-12-20 08:56:41 +00:00
Gadi Haber
7a7a989139 [X86][CLFLUSH]: Adding full coverage of MC encoding for the CLFLUSH isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the CLFLSH and CLFLUSHOPT isa sets.
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, RKSimon, craig.topper, m_zuckerman
Differential Revision: https://reviews.llvm.org/D41331

Change-Id: Ifa643dd52f1b7184c52bc1806038dc74b234fc65
llvm-svn: 321153
2017-12-20 08:28:24 +00:00
Craig Topper
cd13a6054b [X86] Optimize sign extends on index operand to gather/scatter to not sign extend past i32.
The gather instruction will implicitly sign extend to the pointer width, we don't need to further extend it. This can prevent unnecessary splitting in some cases.

There's still an issue that lowering on non-VLX can introduce another sign extend that doesn't get combined with shifts from a lowered sign_extend_inreg.

llvm-svn: 321152
2017-12-20 07:36:59 +00:00
Martin Storsjo
786b1663a9 [AArch64] Implement stack probing for windows
Differential Revision: https://reviews.llvm.org/D41131

llvm-svn: 321150
2017-12-20 06:51:45 +00:00
Craig Topper
a9fd04c09d [X86] Add a missing return to combineGatherScatter after sucessful combine.
Not sure how to test this cause I think the worst that happens is that we don't revisit the node a second time to look for additional combines. We used UpdateNodeOperands so the updating the DAG work was already done.

llvm-svn: 321148
2017-12-20 06:44:50 +00:00
Hiroshi Inoue
019bc11caf [PowerPC] fix a bug in redundant compare elimination
This patch fixes a bug in the redundant compare elimination reported in https://reviews.llvm.org/rL320786 and re-enables the optimization.

The redundant compare elimination assumes that we can replace signed comparison with unsigned comparison for the equality check. But due to the difference in the sign extension behavior we cannot change the opcode if the comparison is against an immediate and the most significant bit of the immediate is one.

Differential Revision: https://reviews.llvm.org/D41385

llvm-svn: 321147
2017-12-20 05:18:19 +00:00
Dan Gohman
a9caee2505 [memcpyopt] Teach memcpyopt to optimize across basic blocks
This teaches memcpyopt to make a non-local memdep query when a local query
indicates that the dependency is non-local. This notably allows it to
eliminate many more llvm.memcpy calls in common Rust code, often by 20-30%.

This is r319482 and r319483, along with fixes for PR35519: fix the 
optimization that merges stores into memsets to preserve cached memdep
info, and fix memdep's non-local caching strategy to not assume that larger
queries are always more conservative than smaller ones.

Fixes PR28958 and PR35519.

Differential Revision: https://reviews.llvm.org/D40802

llvm-svn: 321138
2017-12-20 01:36:25 +00:00
Craig Topper
4e4684aa15 [X86] Improve coverage of fma negations.
llvm-svn: 321137
2017-12-20 01:26:36 +00:00
Craig Topper
c7c526e2c6 [X86] Fix probable typo in fma fneg test.
llvm-svn: 321136
2017-12-20 01:26:35 +00:00
Craig Topper
ff857daeb1 [X86] Remove code from combineSext that looks for MVT::i1 after operation legalization which can never happen.
Type legalization guarantees this to be impossible since MVT::i1 isn't a legal type.

llvm-svn: 321132
2017-12-20 01:00:01 +00:00
Dan Gohman
317619d4ef [WebAssembly] Disable tee_local optimizations when targeting the ELF ABI.
These optimizations depend on the ExplicitLocals pass to lower TEE
instructions, which is disabled in the ELF ABI, so disable them too.

llvm-svn: 321131
2017-12-20 00:59:28 +00:00
Dan Gohman
df3093bdd4 [WebAssembly] Remove an obsolete comment.
llvm-svn: 321127
2017-12-20 00:10:28 +00:00
Adrian McCarthy
88f2a30ff3 Revert "Fix faulty assertion in debug info"
This reverts commit e32def3f7ebe1136b7038336eff56a415a962bf2.

llvm-svn: 321125
2017-12-19 23:34:37 +00:00
Adrian McCarthy
64af24ce75 Fix faulty assertion in debug info
It appears the code uses nullptr to represent a void type in debug metadata,
which led to an assertion failure when building DeltaAlgorithm.cpp with a
self-hosted clang on Windows.

I'm not sure why/if the problem was Windows-specific.

Fixes bug https://bugs.llvm.org/show_bug.cgi?id=35543

Differential Revision: https://reviews.llvm.org/D41264

llvm-svn: 321122
2017-12-19 23:01:17 +00:00
Craig Topper
2f803382dc [X86] Add an assert to indicate that there is only once specific VT allowed at a certain point in LowerMULH.
Helps with code readability a little.

llvm-svn: 321118
2017-12-19 22:38:09 +00:00
Adrian Prantl
b116a83925 Silence a bunch of implicit fallthrough warnings
llvm-svn: 321114
2017-12-19 22:05:25 +00:00
Francis Visoiu Mistrih
7019d036e5 [CodeGen] Move printing MO_BlockAddress operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 321113
2017-12-19 21:47:14 +00:00
Francis Visoiu Mistrih
15126dbcea [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 321112
2017-12-19 21:47:10 +00:00
Francis Visoiu Mistrih
7ddd56e68f [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

Also add support for printing with a null TargetIntrinsicInfo and no
MachineFunction.

llvm-svn: 321111
2017-12-19 21:47:05 +00:00
Francis Visoiu Mistrih
11337d2e4a [CodeGen] Move printing MO_FPImmediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

llvm-svn: 321110
2017-12-19 21:47:00 +00:00
Francis Visoiu Mistrih
f89d2087e2 [CodeGen] Refactor printOffset from MO and MIRPrinter
llvm-svn: 321109
2017-12-19 21:46:55 +00:00
Haicheng Wu
0a31921c96 [CGP] Format. NFC
Clang-format.

llvm-svn: 321107
2017-12-19 20:53:32 +00:00
Matthias Braun
c4c1d5b0b3 TargetLoweringBase: Fix darwinHasSinCos()
Another followup to my refactoring in r321036: Turns out we can end up
with an x86 darwin target that is not macos (simulator triples can look
like i386-apple-ios) so we need the x86/32bit check in all cases.

llvm-svn: 321104
2017-12-19 20:24:12 +00:00
Jonas Devlieghere
122c4697d0 [dwarfdump][test] Add test case for r321064
Verify that -lookup takes a 64-bit address.

llvm-svn: 321101
2017-12-19 19:42:32 +00:00
Mark Searles
c044523a91 [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.
Differential Revision: https://reviews.llvm.org/D41377

llvm-svn: 321100
2017-12-19 19:26:23 +00:00
Haicheng Wu
412f83d1a0 [SeparateConstOffsetFromGEP] Fix a typo. NFC.
do CSE for to => do CSE to

llvm-svn: 321098
2017-12-19 18:49:21 +00:00
Simon Pilgrim
01a1a57616 [X86] Regenerate popcnt tests
llvm-svn: 321093
2017-12-19 18:05:13 +00:00
Amara Emerson
f0ee820679 [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.
This doesn't add legalizer support, just prevents crashing so that we
can gracefully fall back to SDAG.

Fixes PR35690.

llvm-svn: 321091
2017-12-19 17:21:35 +00:00
Nirav Dave
dedadf5587 [DAG] Elide overlapping store
Summary:
Extend overlapping store elision to handle overwrites of stores by
larger stores.

Nontemporal tests have been modified to add memory dependencies to
prevent store elision.

Reviewers: craig.topper, rnk, t.p.northover

Subscribers: javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40969

llvm-svn: 321089
2017-12-19 17:10:56 +00:00
Simon Pilgrim
d4f8c5f95d [X86][AVX512] Attempt target shuffle combining to different types instead of early-out
We try to prevent shuffle combining to value types that would stop the folding of masked operations, but by just returning early, we were failing to try different shuffle types.

The TODOs are all still relevant here to improve codegen but we're lacking test examples.

llvm-svn: 321085
2017-12-19 16:54:07 +00:00
Francis Visoiu Mistrih
1e061bbff4 [CodeGen] Move printing MO_CFIIndex operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

Before this patch we printed "<call frame instruction>" in the debug
output.

llvm-svn: 321084
2017-12-19 16:51:52 +00:00
Francis Visoiu Mistrih
67e6ee03c0 [CFGVPrinter] Fix -dot-cfg-only
The refactoring in r281640 made -dot-cfg-only ignore the "-only" part.

llvm-svn: 321079
2017-12-19 15:20:18 +00:00
Ben Dunbobbin
4a12e46f5f [ThinLTO][C-API] Correct api comments
Negative values never disabled the pruning - they simply set high values for the pruning interval.

The behaviour now is that negative values set the maximum pruning interval (which appears to have been the intention from the start) see https://reviews.llvm.org/D41231.

I have adjusted the comments to reflect this, removed any inaccurate statements, and corrected any typos I spotted in the English.

Differential Revision: https://reviews.llvm.org/D41279

llvm-svn: 321078
2017-12-19 14:49:33 +00:00
Ben Dunbobbin
96703befd6 [Support][CachePruning] Disable cache pruning regression fix
borked by: rL284966 (see: https://reviews.llvm.org/D25730).

Previously, Interval was unsigned (see: CachePruning.h), replacing the type with std::chrono::seconds (which is signed) causes a regression in behaviour because the c-api intends negative values to translate to large positive intervals to *effectively* disable the pruning (see comments on: setCachePruningInterval()).

Differential Revision: https://reviews.llvm.org/D41231

llvm-svn: 321077
2017-12-19 14:42:38 +00:00
Simon Pilgrim
8812d9dc72 [X86] Fix uninitialized variable sanitizer warning from rL321074
llvm-svn: 321076
2017-12-19 14:34:35 +00:00
Haicheng Wu
354d0a92b6 [InlineCost] Skip volatile loads when looking for repeated loads
This is a follow-up fix of r320814.  A test case is also added.

llvm-svn: 321075
2017-12-19 13:42:58 +00:00
Simon Pilgrim
804c89f41f [X86][SSE] Add cpu feature for aggressive combining to variable shuffles
As mentioned in D38318 and D40865, modern Intel processors prefer to combine multiple shuffles to a variable shuffle mask (PSHUFB/VPERMPS etc.) instead of having multiple stage 'fixed' shuffles which put more pressure on Port 5 (at the expense of extra shuffle mask loads).

This patch provides a FeatureFastVariableShuffle target flag for Haswell+ CPUs that prefers combining 2 or more fixed shuffles to a single variable shuffle (default is 3 shuffles).

The long term aim is to drive more of this from schedule data (probably via the MC) but we're not close to being ready for that yet.

Differential Revision: https://reviews.llvm.org/D41323

llvm-svn: 321074
2017-12-19 13:16:43 +00:00
David Green
d048c49d4c [ARM] Register the Thumb2SizeReducePass. NFC
Also adds a simple test case.

llvm-svn: 321072
2017-12-19 12:19:08 +00:00
Pavel Labath
6192ffc4b1 [Support] Add WritableMemoryBuffer class
Summary:
The motivation here is LLDB, where we need to fixup relocations in
mmapped files before their contents can be read correctly.  The
MemoryBuffer class does exactly what we need, *except* that it maps the
file in read-only mode.

WritableMemoryBuffer reuses the existing machinery for opening and
mmapping a file. The only difference is in the argument to the
mapped_file_region constructor -- we create a private copy-on-write
mapping, so that we can make changes to the mapped data, but the changes
aren't carried over to the underlying file.

This patch is based on an initial version by Zachary Turner.

Reviewers: mehdi_amini, rnk, rafael, dblaikie, zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40291

llvm-svn: 321071
2017-12-19 12:15:50 +00:00
Simon Pilgrim
6dd49d11df [X86][SSE] Use (V)PHMINPOSUW for vXi8 SMAX/SMIN/UMAX/UMIN horizontal reductions (PR32841)
Extension to D39729 which performed this for vXi16, with the same bit flipping to handle SMAX/SMIN/UMAX cases, vXi8 UMIN horizontal reductions can be performed.

This makes use of the fact that by performing a pair-wise i8 SHUFFLE/UMIN before PHMINPOSUW, we both get the UMIN of each pair but also zero-extend the upper bits ready for v8i16.

Differential Revision: https://reviews.llvm.org/D41294

llvm-svn: 321070
2017-12-19 12:02:40 +00:00
Francis Visoiu Mistrih
859334a80d Fix: [YAML] Always double quote UTF-8 characters
llvm-svn: 321069
2017-12-19 11:59:28 +00:00
Francis Visoiu Mistrih
e1d5d5ba4e [YAML] Always double quote UTF-8 characters
llvm-svn: 321068
2017-12-19 11:51:05 +00:00
Simon Dardis
9c259722df [mips] Handle the emission of microMIPSr6 sll instruction when used as a nop.
This instruction is encoded as zero, so we have handle that case when checking
for unimplemented opcodes when producing the encoding for an instruction.

llvm-svn: 321066
2017-12-19 11:16:22 +00:00
Jonas Devlieghere
c562c1f132 [dwarfdump] Lookup needs to be an unsigned long long parameter.
Before this patch, dwarfdump's lookup parameter only accepts unsigned.
Given that for many current platforms the load address already exceeds
unsigned (e.g. arm64 w/ 0x100000000), dwarfdump needs an unsigned long
long parameter.

Patch by: Dr. Michael 'Mickey' Lauer <mickey@vanille-media.de>

llvm-svn: 321064
2017-12-19 09:45:26 +00:00
Max Kazantsev
73d7a6bc49 [JumpThreading] Restrict PRE across instructions that don't pass control to successors
PRE in JumpThreading should not be able to hoist copy of non-speculable loads across
instructions that don't always transfer execution to their successors, otherwise they may
introduce an unsafe load which otherwise would not be executed.

The same problem for GVN was fixed as rL316975.

Differential Revision: https://reviews.llvm.org/D40347

llvm-svn: 321063
2017-12-19 09:10:21 +00:00
Igor Laevsky
aba02c9095 [FuzzMutate] Don't crash when mutator is unable to find operation
Differential Revision: https://reviews.llvm.org/D41009

llvm-svn: 321062
2017-12-19 08:52:51 +00:00
Bjorn Steinbrink
feb288b9a0 Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes()
Reviewers: rnk, hfinkel, efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41355

llvm-svn: 321061
2017-12-19 08:46:46 +00:00
Craig Topper
b64e60f4ce [X86] Don't extend v16i8 non-uniform shifts to v16i32 if we have BWI. Use v16i16 instead.
BWI supports shifting by word amounts. Even if VLX isn't support we can still widen to v32i16 and extract the lower half. For SKX its preferrable to not use 512-bit vector if we can.

llvm-svn: 321059
2017-12-19 06:59:10 +00:00
Craig Topper
f6641677a8 [X86] Use a specific list of MVTs in combineShiftRightArithmetic instead of iterating over every integer VT and checking their size.
Previously, we were checking for MVTs with sizes betwen 8 and 64 which only includes i8, i16, i32, and i64 today. But I don't think we should assume that and should list the types that are legal for x86. I also don't think we need i64 since type legalization is guaranteed to split those up.

llvm-svn: 321058
2017-12-19 06:29:00 +00:00