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Author SHA1 Message Date
Chris Lattner
5d982469f8 add comments. 
llvm-svn: 135164
 2011-07-14 18:12:44 +00:00
Chris Lattner
b3458315d4 consolidate GlobalValue::isDeclaration into one 
non-virtual function.

llvm-svn: 135163
 2011-07-14 18:10:41 +00:00
Jim Grosbach
ebbd82a248 ARM ISB assembly parsing tests. 
llvm-svn: 135158
 2011-07-14 18:02:25 +00:00
Chris Lattner
41059ff010 code cleanup 
llvm-svn: 135157
 2011-07-14 18:01:49 +00:00
Jim Grosbach
9bbc2007df ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
 2011-07-14 18:00:31 +00:00
Benjamin Kramer
a6129829fa Change Intrinsic::getDeclaration and friends to take an ArrayRef. 
llvm-svn: 135154
 2011-07-14 17:45:39 +00:00
Chris Lattner
f98f70f2f2 add a couple more missing C api, patch by Vitaly Lugovskiy! 
llvm-svn: 135151
 2011-07-14 16:20:28 +00:00
Richard Osborne
d73d21c487 Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUE 
instructions.

llvm-svn: 135146
 2011-07-14 14:03:48 +00:00
Frits van Bommel
5017656bef Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector. 
llvm-svn: 135145
 2011-07-14 11:44:09 +00:00
Nadav Rotem
b93249b1e7 [VECTOR-SELECT] 
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.

llvm-svn: 135144
 2011-07-14 11:11:14 +00:00
Nadav Rotem
1a0334b49c Add assertion for the chain value type 
llvm-svn: 135143
 2011-07-14 10:37:54 +00:00
Jay Foad
471e6f62b4 Mention all API changes I've made since 2.9 was branched. 
llvm-svn: 135142
 2011-07-14 09:19:05 +00:00
Eric Christopher
be21240f6f Add a testcase for r135123. 
Part of rdar://9761830

llvm-svn: 135133
 2011-07-14 06:23:09 +00:00
Chris Lattner
bd1cea5fe4 add C api for hte new type system rewrite API. Patch by Vitaly Lugovskiy! 
llvm-svn: 135132
 2011-07-14 05:53:17 +00:00
Evan Cheng
3d2be55d6c Unfortunately several files in MC are badly violating layering rule by using 
TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.

This patch is but one small step towards fixing this. 500 more steps to go. :-(

llvm-svn: 135131
 2011-07-14 05:43:07 +00:00
Jakob Stoklund Olesen
b0af7bda8d Reapply r135121 with a fixed copy constructor. 
Original commit message:

Count references to interference cache entries.

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135130
 2011-07-14 05:35:11 +00:00
Devang Patel
39f6e21de3 Simplify. 
llvm-svn: 135127
 2011-07-14 01:52:45 +00:00
Benjamin Kramer
1cab6179ab Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. 
llvm-svn: 135126
 2011-07-14 01:38:42 +00:00
Devang Patel
1856a523ea Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as much as possible. 
llvm-svn: 135124
 2011-07-14 01:14:57 +00:00
Eric Christopher
e84fe67d4f Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A 
Fixes rdar://9761830

llvm-svn: 135123
 2011-07-14 01:12:15 +00:00
Jakob Stoklund Olesen
718e76d4dd Revert r135121 which broke a gcc-4.2 builder. 
llvm-svn: 135122
 2011-07-14 00:58:38 +00:00
Jakob Stoklund Olesen
7d17ec883e Count references to interference cache entries. 
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135121
 2011-07-14 00:31:14 +00:00
Eli Friedman
a1db9f2fd5 Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. 
llvm-svn: 135120
 2011-07-14 00:22:31 +00:00
Jim Grosbach
76bd4e6f75 ARM tests for EOR instruction parsing and encoding. 
llvm-svn: 135119
 2011-07-14 00:22:21 +00:00
Devang Patel
cb54f643e9 Simplify. Compile unit check inside hasValidLocation() did not add any value. 
llvm-svn: 135118
 2011-07-14 00:20:24 +00:00
Jim Grosbach
fe9c954c0f Remove duplicate tests. 
llvm-svn: 135117
 2011-07-14 00:19:19 +00:00
Jim Grosbach
4b63d59acb ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
 2011-07-14 00:18:13 +00:00
Jakob Stoklund Olesen
b1011cf255 Reapply r135074 and r135080 with a fix. 
The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.

The correct fix here is to use reference counts on the cache entries.
Coming up.

llvm-svn: 135113
 2011-07-14 00:17:10 +00:00
Jim Grosbach
2ee8287c62 DMB instalias needs the same predicate as the instruction. 
llvm-svn: 135112
 2011-07-14 00:10:26 +00:00
Devang Patel
8d1207dc18 Fix typo in DEBUG message. 
llvm-svn: 135111
 2011-07-14 00:04:53 +00:00
Devang Patel
b9fe59ad12 Add DEBUG messages. 
llvm-svn: 135110
 2011-07-14 00:03:58 +00:00
Jim Grosbach
5a96cebd81 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
 2011-07-13 23:40:38 +00:00
Jim Grosbach
3eb4f0de5e Update comments. These are for assembler, too. 
llvm-svn: 135107
 2011-07-13 23:33:10 +00:00
Owen Anderson
c68f12ff30 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. 
llvm-svn: 135106
 2011-07-13 23:22:26 +00:00
Bill Wendling
e896e46a8c Add code to handle a "frameless" unwind stack. 
The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

llvm-svn: 135103
 2011-07-13 23:03:31 +00:00
Jim Grosbach
c0ec4205e2 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
 2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes
f29783ee55 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. 
llvm-svn: 135099
 2011-07-13 22:28:55 +00:00
Jim Grosbach
25a4b8922d ARM parsing and encoding tests for CMN/CMP. 
llvm-svn: 135098
 2011-07-13 22:26:58 +00:00
David Greene
a72634bcb8 struct Init -> class Init 
Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

llvm-svn: 135097
 2011-07-13 22:25:51 +00:00
Jakob Stoklund Olesen
5102a957a1 Revert r135074 and r135080. They broke clamscan. 
llvm-svn: 135096
 2011-07-13 22:20:09 +00:00
Jim Grosbach
d5e74991f0 Shuffle ARM assembly tests a bit. 
llvm-svn: 135095
 2011-07-13 22:19:10 +00:00
Jim Grosbach
c9e49f3b51 Revert 135093. Think-o. 
llvm-svn: 135094
 2011-07-13 22:06:11 +00:00
Jim Grosbach
545a3f4802 Correct range for thumb co-processor immediate 
llvm-svn: 135093
 2011-07-13 22:03:11 +00:00
Jim Grosbach
fd2ebb4552 Range checking for CDP[2] immediates. 
llvm-svn: 135092
 2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
c0401dddf7 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more 
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088
 2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes
b98f50da03 The target specific node PANDN name is misleading. That happens because 
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

llvm-svn: 135087
 2011-07-13 21:36:47 +00:00
Jim Grosbach
76ba2e7e9c Cleanup Thumb co-processor instructions a bit. 
Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085
 2011-07-13 21:35:10 +00:00
Eli Friedman
30d557cc28 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. 
<rdar://problem/9763308>

llvm-svn: 135084
 2011-07-13 21:29:53 +00:00
Jim Grosbach
385d9a3e57 Parameterize away the ARM T1Cop class. 
llvm-svn: 135082
 2011-07-13 21:17:59 +00:00
Jim Grosbach
d3b15141b8 Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
 2011-07-13 21:14:23 +00:00