Commit Graph

178837 Commits

Author SHA1 Message Date
James Henderson
6982be23a3 [llvm-objdump]Split section-filter.test in two to remove X86 dependency
This allows the generic parts of section-filter.test to be tested on all
targets. The X86-specific parts have been moved to another test.

llvm-svn: 360904
2019-05-16 14:49:10 +00:00
Matt Arsenault
b6b7acf7ed AMDGPU: Assume xnack is enabled by default
This is the conservatively correct default. It is always safe to
assume xnack is enabled, but not the converse.

Introduce a feature to blacklist targets where xnack can never be
meaningfully enabled. I'm not sure the targets this is applied to is
100% correct.

llvm-svn: 360903
2019-05-16 14:48:34 +00:00
Stephen Tozer
62b6b24e6d Resubmit: [Salvage] Change salvage debug info implementation to use DW_OP_LLVM_convert where needed
Fixes issue: https://bugs.llvm.org/show_bug.cgi?id=40645

Previously, LLVM had no functional way of performing casts inside of a
DIExpression(), which made salvaging cast instructions other than Noop casts
impossible. With the recent addition of DW_OP_LLVM_convert this salvaging is
now possible, and so can be used to fix the attached bug as well as any cases
where SExt instruction results are lost in the debugging metadata. This patch
introduces this fix by expanding the salvage debug info method to cover these
cases using the new operator.

Differential revision: https://reviews.llvm.org/D61184

llvm-svn: 360902
2019-05-16 14:41:01 +00:00
Fangrui Song
9c402973dc [llvm-objdump] Add "REQUIES: x86-registered-target" to section-filter.test after rL360893
Appease the hexagon buildbot that doesn't build X86. Disassemblers
require Target/X86 support.

llvm-svn: 360901
2019-05-16 14:40:31 +00:00
Sanjay Patel
d7d961c490 [InstSimplify] fold fcmp (minnum, X, C1), C2
minnum(X, LesserC) == C --> false
   minnum(X, LesserC) >= C --> false
   minnum(X, LesserC) >  C --> false
   minnum(X, LesserC) != C --> true
   minnum(X, LesserC) <= C --> true
   minnum(X, LesserC) <  C --> true

maxnum siblings will follow if there are no problems here.

We should be able to perform some other combines when the constants
are equal or greater-than too, but that would go in instcombine.

We might also generalize this by creating an FP ConstantRange
(similar to what we do for integers).

Differential Revision: https://reviews.llvm.org/D61691

llvm-svn: 360899
2019-05-16 14:03:10 +00:00
Xing Xue
c444d8dd91 Fixes for builds that require strict X/Open and POSIX compatiblity
Summary:
- Use alternative to MAP_ANONYMOUS for allocating mapped memory if it isn't available
- Use strtok_r instead of strsep as part of getting program path
- Don't try to find the width of a terminal using "struct winsize" and TIOCGWINSZ on POSIX builds. These aren't defined under POSIX (even though some platforms make them available when they shouldn't), so just check if we are doing a X/Open or POSIX compliant build first.

Author: daltenty

Reviewers: hubert.reinterpretcast, xingxue, andusy

Reviewed By: hubert.reinterpretcast

Subscribers: MaskRay, jsji, hiraditya, kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61326

llvm-svn: 360898
2019-05-16 14:02:13 +00:00
Alex Bradbury
86134fbb27 [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
This is in preparation for emitting CFI directives.

llvm-svn: 360897
2019-05-16 13:56:23 +00:00
Xing Xue
2c3562fc12 [tests][go]Add -stdlib=libc++ to build GO test if LLVM is built with libc++
When libc++ is used to build LLVM libraries, these libraries have dependencies on libc++ and C++ STL signatures in these libraries are corresponding to libc++ implementation. Therefore, -stdlib=libc++ is required on the C++ compiler command for building GO tests that link with these LLVM libraries.

Reviewers: hubert.reinterpretcast, sfertile, amyk, EricWF

Reviewed By: sfertile, hubert.reinterpretcast

Subscribers: jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61900

llvm-svn: 360895
2019-05-16 13:32:55 +00:00
Adhemerval Zanella
101145b734 [AArch64] Handle ISD::LROUND and ISD::LLROUND
This patch optimizes ISD::LROUND and ISD::LLROUND to fcvtas
instruction. It currently only handles the scalar version.

llvm-svn: 360894
2019-05-16 13:30:18 +00:00
James Henderson
2e4337f322 [llvm-objdump]Improve testing of some switches #1
This is the first in a set of patches I have to improve testing of
llvm-objdump. This patch targets --all-headers, --section, and
--full-contents. In the --section case, it deletes a pre-canned binary
which is only used by the one test and replaces it with yaml.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D61941

llvm-svn: 360893
2019-05-16 13:28:36 +00:00
Fangrui Song
169d5671df Recommit [Object] Change object::SectionRef::getContents() to return Expected<StringRef>
r360876 didn't fix 2 call sites in clang.

Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now.

Follow-up of D61781.

llvm-svn: 360892
2019-05-16 13:24:04 +00:00
Adhemerval Zanella
c00c3084e9 [CodeGen] Add lround/llround builtins
This patch add the ISD::LROUND and ISD::LLROUND along with new
intrinsics.  The changes are straightforward as for other
floating-point rounding functions, with just some adjustments
required to handle the return value being an interger.

The idea is to optimize lround/llround generation for AArch64
in a subsequent patch.  Current semantic is just route it to libm
symbol.

llvm-svn: 360889
2019-05-16 13:15:27 +00:00
Matt Arsenault
082b98432d GlobalISel: Add buildFMA to MachineIRBuilder
llvm-svn: 360888
2019-05-16 13:04:20 +00:00
Matt Arsenault
5fe7f3e187 RegAllocFast: Improve hinting heuristic
Trace through multiple COPYs when looking for a physreg source. Add
hinting for vregs that will be copied into physregs (we only hinted
for vregs getting copied to a physreg previously).  Give hinted a
register a bonus when deciding which value to spill.  This is part of
my rewrite regallocfast series. In fact this one doesn't even have an
effect unless you also flip the allocation to happen from back to
front of a basic block. Nonetheless it helps to split this up to ease
review of D52010

Patch by Matthias Braun

llvm-svn: 360887
2019-05-16 12:50:39 +00:00
Clement Courbet
493956af53 [DominatorTree] Print roots unconditionally in print().
Summary:
This came up in a debugging session. I was failing to update the root of
the tree, and got during verification:

```
DominatorTree is different than a freshly computed one!
        Current:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
  [1] %"entry+land.rhs.i" {4294967295,4294967295} [0]
    [2] %opeq1.exit {4294967295,4294967295} [1]

        Freshly computed tree:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
  [1] %"entry+land.rhs.i" {4294967295,4294967295} [0]
    [2] %opeq1.exit {4294967295,4294967295} [1]
```

We now print:

```
DominatorTree is different than a freshly computed one!
        Current:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
  [1] %"entry+land.rhs.i" {4294967295,4294967295} [0]
    [2] %opeq1.exit {4294967295,4294967295} [1]
Roots: <badref>

        Freshly computed tree:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
  [1] %"entry+land.rhs.i" {4294967295,4294967295} [0]
    [2] %opeq1.exit {4294967295,4294967295} [1]
Roots: %"entry+land.rhs.i"
```

Reviewers: kuhar, asbirlea

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61999

llvm-svn: 360886
2019-05-16 12:48:56 +00:00
Roman Lebedev
4b83110a49 [NFC] Fixup FileCheck option name in tests added in rL360881
llvm-svn: 360884
2019-05-16 12:39:34 +00:00
Roman Lebedev
01a1081d7a [NFC][CodeGen] Add some more tests for pulling binops through shifts
The ashr variant may see relaxation in https://reviews.llvm.org/D61918

llvm-svn: 360881
2019-05-16 12:26:53 +00:00
Matt Arsenault
13e2bca05f GlobalISel: Add buildXor/buildNot
llvm-svn: 360880
2019-05-16 12:23:04 +00:00
Matt Arsenault
de8e2a4b00 GlobalISel: Add DstOp version of buildIntrinsic
llvm-svn: 360879
2019-05-16 12:22:56 +00:00
Hans Wennborg
85cc2962c2 Revert r360876 "[Object] Change object::SectionRef::getContents() to return Expected<StringRef>"
It broke the Clang build, see llvm-commits thread.

> Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now.
>
> Follow-up of D61781.

llvm-svn: 360878
2019-05-16 12:08:34 +00:00
Matt Arsenault
f1fd82673f AMDGPU/GlobalISel: Correct regbank for 1-bit and/or/xor
Bool values should use the scc/vcc regbank since r350611.

llvm-svn: 360877
2019-05-16 12:06:41 +00:00
Fangrui Song
e0aa0a19b4 [Object] Change object::SectionRef::getContents() to return Expected<StringRef>
Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now.

Follow-up of D61781.

llvm-svn: 360876
2019-05-16 11:33:48 +00:00
Cullen Rhodes
7ef8584543 [AArch64][SVE2] Asm: implement CMLA/SQRDCMLAH instructions
Summary:
This patch adds support for the indexed and unpredicated vectors forms
of the CMLA and SQRDCMLAH instructions.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D61906

llvm-svn: 360871
2019-05-16 09:42:22 +00:00
Cullen Rhodes
2eaf0460bc [AArch64][SVE2] Asm: implement CDOT instruction
Summary:
The complex DOT instructions perform a dot-product on quadtuplets from
two source vectors and the resuling wide real or wide imaginary is
accumulated into the destination register. The instructions come in two
forms:

Vector form, e.g.
  cdot z0.s, z1.b, z2.b, #90    - complex dot product on four 8-bit quad-tuplets,
                                  accumulating results in 32-bit elements. The
                                  complex numbers in the second source vector are
                                  rotated by 90 degrees.

  cdot z0.d, z1.h, z2.h, #180   - complex dot product on four 16-bit quad-tuplets,
                                  accumulating results in 64-bit elements.
                                  The complex numbers in the second source
                                  vector are rotated by 180 degrees.

Indexed form, e.g.
  cdot z0.s, z1.b, z2.b[3], #0  - complex dot product on four 8-bit quad-tuplets,
                                  with specified quadtuplet from second source vector,
                                  accumulating results in 32-bit elements.
  cdot z0.d, z1.h, z2.h[1], #0  - complex dot product on four 16-bit quad-tuplets,
                                  with specified quadtuplet from second source vector,
                                  accumulating results in 64-bit elements.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer, rovka

Differential Revision: https://reviews.llvm.org/D61903

llvm-svn: 360870
2019-05-16 09:33:44 +00:00
Cullen Rhodes
f96af16cbf [AArch64][SVE2] Asm: add unpredicated integer multiply instructions
Summary:
Add support for the following instructions:

  * MUL (indexed and unpredicated vectors forms)
  * SQDMULH (indexed and unpredicated vectors forms)
  * SQRDMULH (indexed and unpredicated vectors forms)
  * SMULH (unpredicated, predicated form added in SVE)
  * UMULH (unpredicated, predicated form added in SVE)
  * PMUL (unpredicated)

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer, rovka

Differential Revision: https://reviews.llvm.org/D61902

llvm-svn: 360867
2019-05-16 09:07:26 +00:00
Fangrui Song
aeef0e205d Add Triple::isPPC64()
llvm-svn: 360864
2019-05-16 08:31:22 +00:00
George Rimar
f62dc93eff [llvm-readobj] - Revert r360676 partially. NFC.
In the r360676 "Apply clang format. NFC" I applied clang-format
for whole ELFDumper.cpp. It caused a little discussion,
one of the points mentioned was that previously nicely lined up
tables are not so nice now.

This patch reverts them.

llvm-svn: 360860
2019-05-16 06:22:51 +00:00
Clement Courbet
e9b22834e6 Reland r360771 "[MergeICmps] Simplify the code."
This revision does not seem to be the culprit.

llvm-svn: 360859
2019-05-16 06:18:02 +00:00
Igor Kudrin
f174188313 [IRMover] Improve diagnostic messages for conflicting metadata
This does the similar for error messages as rL344011 has done for warnings.

With llvm::lto::LTO, the error might appear when LTO::run() is executed.
In that case, the calling code cannot know which module causes the error
and, subsequently, cannot hint the user.

Differential Revision: https://reviews.llvm.org/D61880

llvm-svn: 360857
2019-05-16 05:23:13 +00:00
Matt Arsenault
c12f7508a5 GlobalISel: Add buildFConstant for APFloat
llvm-svn: 360853
2019-05-16 04:09:06 +00:00
Matt Arsenault
acf98dc474 GlobalISel: Add some FP instructions to MachineIRBuilder
This makes FP legalization code more convenient.

llvm-svn: 360852
2019-05-16 04:08:55 +00:00
Matt Arsenault
fd2428f698 GlobalISel: Fix indentation
llvm-svn: 360851
2019-05-16 04:08:46 +00:00
Matt Arsenault
d0fc07f9c6 GlobalISel: Add G_FCOPYSIGN
llvm-svn: 360850
2019-05-16 04:08:39 +00:00
Matt Arsenault
5e77fe1040 Fix missing const
llvm-svn: 360849
2019-05-16 04:08:25 +00:00
Yevgeny Rouban
0306ca2838 Fix prof branch_weights in entry_counts_missing_dbginfo.ll test
Removed extra parameter from !prof branch_weights metadata of
a call instruction according to the spec.

Differential Revision: https://reviews.llvm.org/D61932

llvm-svn: 360843
2019-05-16 03:39:09 +00:00
Eric Christopher
4f43643257 Fix typo in comment of CSAction -> Action.
llvm-svn: 360834
2019-05-16 01:07:54 +00:00
Lang Hames
a05660fcc0 [ORC] Modify DenseMap hashing for SymbolStringPtrs.
Modifies the DenseMapInfo<SymbolStringPtr>::getHashValue method to take its
argument by const-ref rather than by value (to avoid unnecessary ref-counting
operations) and to defer to DenseMapInfo<void*> for the hash value computation
(since SymbolStringPtrs are just pointers under the hood).

llvm-svn: 360831
2019-05-16 00:21:10 +00:00
Lang Hames
3d30a3c885 [JITLink][MachO] Use getSymbol64TableEntry for 64-bit MachO files.
Fixes a think-o. No test case: The nlist and nlist64 data structures happen to
line up for this field, so there's no way to construct a failing test case.

llvm-svn: 360830
2019-05-16 00:21:07 +00:00
Vitaly Buka
410ce9e6a9 Fix GN build
llvm-svn: 360829
2019-05-16 00:19:37 +00:00
Craig Topper
8b23ddf95e [X86] Delay creating index register negations during address matching until after we know for sure the match will succeed
If we're trying to match an LEA, its possible the LEA match will be deemed unprofitable. In which case the negation we created in matchAddress would be left dangling in the SelectionDAG. This could artificially increase use counts for other nodes in the DAG. Though I don't have an example of that. But it just seems like bad form to have dangling nodes in isel.

Differential Revision: https://reviews.llvm.org/D61047

llvm-svn: 360823
2019-05-15 21:59:53 +00:00
Reid Kleckner
5a358de7b9 [codeview] Fix SDNode representation of annotation labels
Before this change, they were erroneously constructed with the EH_LABEL
SDNode opcode, which caused other passes to interact with them in
incorrect ways. See the FIXME about fastisel that this addresses in the
existing test case.

Fixes PR41890

llvm-svn: 360818
2019-05-15 21:46:05 +00:00
Simon Atanasyan
ff2428283a [mips] Use range-based for loops. NFC
llvm-svn: 360817
2019-05-15 21:26:25 +00:00
Mandeep Singh Grang
4fdc3d2e09 [AArch64] only indicate CFI on Windows if we emitted CFI
Summary:
Otherwise, we emit directives for CFI without any actual CFI opcodes to
go with them, which causes tools to malfunction.  The technique is
similar to what the x86 backend already does.

Fixes https://bugs.llvm.org/show_bug.cgi?id=40876

Patch by: froydnj (Nathan Froyd)

Reviewers: mstorsjo, eli.friedman, rnk, mgrang, ssijaric

Reviewed By: rnk

Subscribers: javed.absar, kristof.beyls, llvm-commits, dmajor

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61960

llvm-svn: 360816
2019-05-15 21:23:41 +00:00
Craig Topper
9be0608242 [X86] Strengthen type constraints on some specialized X86 ISD opcodes that don't have any flexibility. NFC
These particular instructions only operate on 128-bit vectors and have no wider equivalents. And the
element size is always known.

One could argue that MOVSS/MOVSD could be merged, but that's probably disruptive to code in
X86ISelLowering and probably low value.

llvm-svn: 360815
2019-05-15 21:16:28 +00:00
Roman Lebedev
b500c0beb0 [NFC][InstCombine] Add some more tests for pulling binops through shifts
The ashr variant may see relaxation in https://reviews.llvm.org/D61938

llvm-svn: 360814
2019-05-15 21:15:44 +00:00
Reid Kleckner
69bcd5e9da [codeview] Finish support for reading and writing S_ANNOTATION records
Implement dumping via llvm-pdbutil and llvm-readobj.

llvm-svn: 360813
2019-05-15 20:53:39 +00:00
Cameron McInally
bb838fb363 Revert llvm-svn: 360807
Somehow submitted this patch twice.

llvm-svn: 360812
2019-05-15 20:48:50 +00:00
Cameron McInally
1b0f13faaf Pre-commit unary fneg tests to InstSimplify
llvm-svn: 360808
2019-05-15 20:27:37 +00:00
Cameron McInally
d81022dd14 Add unary fneg to InstSimplify/fp-nan.ll
llvm-svn: 360807
2019-05-15 20:27:35 +00:00
Pete Couperus
d35b2c5e10 Uncomment LLVM_FALLTHROUGH.
llvm-svn: 360798
2019-05-15 19:46:17 +00:00