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Author SHA1 Message Date
Bob Wilson
8f0cf81f09 Add VLD1-lane testcases for quad-register types. 
llvm-svn: 117975
 2010-11-01 23:40:46 +00:00
Bill Wendling
dd4216420a Missed reverting this bit. 
llvm-svn: 117971
 2010-11-01 23:17:54 +00:00
Bill Wendling
37c9af176d Minor cleanup. 
llvm-svn: 117969
 2010-11-01 23:11:22 +00:00
Chris Lattner
1bdba218ef give MatchableInfo::Operand a constructor 
llvm-svn: 117968
 2010-11-01 23:08:02 +00:00
Chris Lattner
f94c2b782a rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Jakob Stoklund Olesen
0ed56c87e4 Add kill flag verification. 
At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.

llvm-svn: 117960
 2010-11-01 21:51:31 +00:00
Jakob Stoklund Olesen
78ba455b51 Update kill flags while rewriting instructions after splitting. 
llvm-svn: 117959
 2010-11-01 21:51:29 +00:00
Bill Wendling
69e7c09c32 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Bill Wendling
af717e3c58 Use ARM-style comments. 
llvm-svn: 117955
 2010-11-01 21:16:39 +00:00
Owen Anderson
47f0efad86 When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low 
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953
 2010-11-01 21:08:20 +00:00
Chris Lattner
b0ac93cf15 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Bill Wendling
4340c9449a When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Jakob Stoklund Olesen
66012df062 Don't assign new registers created during a split to the same stack slot, but 
give them individual stack slots once the are actually spilled.

llvm-svn: 117945
 2010-11-01 19:49:57 +00:00
Jakob Stoklund Olesen
b4a55702b7 Add basic LiveStacks verification. 
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944
 2010-11-01 19:49:52 +00:00
Owen Anderson
09920faec7 Use ARM-style comment syntax. 
llvm-svn: 117941
 2010-11-01 18:33:37 +00:00
Bob Wilson
a9c593e696 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Owen Anderson
dbba9bcc36 Covert this test to .s form. 
llvm-svn: 117939
 2010-11-01 18:30:39 +00:00
Owen Anderson
38af2df6e5 Convert this test to .s form. 
llvm-svn: 117938
 2010-11-01 18:26:43 +00:00
Owen Anderson
8d4bfde002 Covert this test to .s form. 
llvm-svn: 117937
 2010-11-01 18:13:11 +00:00
Jim Grosbach
acc28d1b2a Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Owen Anderson
d5757a8585 Covert this test to .s form. 
llvm-svn: 117935
 2010-11-01 18:03:16 +00:00
Rafael Espindola
eff645265a Fix test. 
llvm-svn: 117932
 2010-11-01 17:10:53 +00:00
Jim Grosbach
53d2661c60 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Rafael Espindola
2f114f8430 Write the line info to .debug_line. 
llvm-svn: 117930
 2010-11-01 17:07:14 +00:00
Jim Grosbach
76910aa62f Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach
2605b2b54f trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Rafael Espindola
5571ce5ed4 Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it. 
llvm-svn: 117925
 2010-11-01 16:27:31 +00:00
Jim Grosbach
311aa5e22f The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Rafael Espindola
a7f92c500c Add support for .value. 
llvm-svn: 117922
 2010-11-01 15:29:07 +00:00
Rafael Espindola
7a38cb0144 Implement .weakref. 
llvm-svn: 117911
 2010-11-01 14:28:48 +00:00
Bill Wendling
da3d0ce7b5 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Bill Wendling
a59bb03780 More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the 
peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905
 2010-11-01 05:59:43 +00:00
Bill Wendling
70856991c5 The testcase is now XFAILed. Sorry about the breakage. 
llvm-svn: 117904
 2010-11-01 05:50:55 +00:00
Bill Wendling
bfdbe6b369 Disable because peephole is disabled. 
llvm-svn: 117903
 2010-11-01 05:48:44 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Owen Anderson
ccef9fc4fc Convert this test to .s form. 
llvm-svn: 117900
 2010-11-01 05:23:58 +00:00
Chris Lattner
c211fb27e2 rename InstructionInfo -> MatchableInfo since it now 
represents InstAliases as well.  Rename 
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).

llvm-svn: 117899
 2010-11-01 05:06:45 +00:00
Chris Lattner
8105d0ff81 refactor initialization of InstructionInfo to be sharable between 
instructions and InstAliases.  Start creating InstructionInfo's
for Aliases.

llvm-svn: 117898
 2010-11-01 04:53:48 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
87c0d54fed refactor InstructionInfo to not have a pointer to CodeGenInstruction 
member, and make isAssemblerInstruction() a method (pushing some code
around inside it).

llvm-svn: 117895
 2010-11-01 04:34:44 +00:00
Chris Lattner
c746d18c42 define a new CodeGenInstAlias. It has an asmstring and operand list for now, 
todo: the result field.

llvm-svn: 117894
 2010-11-01 04:05:41 +00:00
Chris Lattner
45b1a1649c factor the operand list (and related fields/operations) out of 
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
 2010-11-01 04:03:32 +00:00
Chris Lattner
88f746114f avoid needless throw/catch/rethrow, stringref'ize some simple stuff. 
llvm-svn: 117892
 2010-11-01 03:19:09 +00:00
Chris Lattner
d57d9e862d eliminate the old InstFormatName which is always "AsmString", 
simplify CodeGenInstruction. No functionality change.

llvm-svn: 117891
 2010-11-01 02:15:23 +00:00
Chris Lattner
a8d1d91f41 all predicates on an MnemonicAlias must be AssemblerPredicates. 
llvm-svn: 117890
 2010-11-01 02:09:21 +00:00
Chris Lattner
22f9108208 change the singleton register handling code to be based on Record*'s 
instead of strings, simplifying it.

llvm-svn: 117889
 2010-11-01 01:47:07 +00:00
Chris Lattner
359e5c93e8 Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of 
argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.

llvm-svn: 117888
 2010-11-01 01:37:30 +00:00
Chris Lattner
0a33c519da move FlattenVariants out of AsmMatcherEmitter into a shared 
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.

llvm-svn: 117886
 2010-11-01 01:07:14 +00:00