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Author SHA1 Message Date
Johnny Chen
727c71d8ac Added a bunch of saturating add/subtract instructions for disassembly only. 
llvm-svn: 96063
 2010-02-13 01:21:01 +00:00
Chris Lattner
d4fe983f23 rip out the 'heinous' x86 MCCodeEmitter implementation. 
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059
 2010-02-13 00:49:29 +00:00
Chris Lattner
5b01ab848c remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Bob Wilson
5d66f81412 Besides removing phi cycles that reduce to a single value, also remove dead 
phi cycles.  Adjust a few tests to keep dead instructions from being optimized
away.  This (together with my previous change for phi cycles) fixes Apple
radar 7627077.

llvm-svn: 96057
 2010-02-13 00:31:44 +00:00
Dan Gohman
1e93b1c022 Override dominates and properlyDominates for SCEVAddRecExpr, as a 
SCEVAddRecExpr doesn't necessarily dominate blocks merely dominated
by all of its operands. This fixes an abort compiling 403.gcc.

llvm-svn: 96056
 2010-02-13 00:19:39 +00:00
Daniel Dunbar
4ef0be5df5 MC/X86: Push immediate operands as immediates not expressions when possible. 
llvm-svn: 96055
 2010-02-13 00:17:21 +00:00
Jeffrey Yasskin
963eee9ee1 Make PassRegistrar thread-safe since it can be modified by code running in 
separate LLVMContexts.

llvm-svn: 96051
 2010-02-13 00:03:17 +00:00
Chris Lattner
1d25e3978d Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
 2010-02-12 23:54:57 +00:00
Chris Lattner
c80a6de0a9 add some disassemble testcases for weird instructions 
llvm-svn: 96045
 2010-02-12 23:46:48 +00:00
Sean Callanan
21a160f4bf Reworked the Intel disassembler to support instructions 
whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction.  Commented out the special
casing of VMCALL, which is the first instruction to use
this special form.  While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler. 

llvm-svn: 96043
 2010-02-12 23:39:46 +00:00
Chris Lattner
4170bb81da implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.

llvm-svn: 96040
 2010-02-12 23:24:09 +00:00
Dale Johannesen
08f0ab42b8 Add the problem I just hacked around in 96015/96020. 
The solution there produces correct code, but is seriously
deficient in several ways.

llvm-svn: 96039
 2010-02-12 23:16:24 +00:00
Chris Lattner
946403d05f give MCCodeEmitters access to the current MCContext. 
llvm-svn: 96038
 2010-02-12 23:12:47 +00:00
Jeffrey Yasskin
72e77cf286 Make JIT::runFunction clean up the generated stub function. 
Patch by Shivram K!

llvm-svn: 96037
 2010-02-12 23:05:31 +00:00
Chris Lattner
e90d092fd7 implement infrastructure to support fixups for rip-rel 
addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036
 2010-02-12 23:00:36 +00:00
Johnny Chen
d36727232c Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032
 2010-02-12 22:53:19 +00:00
Chris Lattner
0a7654c7c9 pull the rip-relative addressing mode case up early. 
llvm-svn: 96031
 2010-02-12 22:47:55 +00:00
Chris Lattner
3df1321651 fixme resolved! 
llvm-svn: 96029
 2010-02-12 22:39:06 +00:00
Chris Lattner
1e01ac75bc start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls. 
llvm-svn: 96028
 2010-02-12 22:36:47 +00:00
Bob Wilson
881d06c0b9 Fix a comment typo. 
llvm-svn: 96027
 2010-02-12 22:34:54 +00:00
Chris Lattner
f1f926247f enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026
 2010-02-12 22:27:07 +00:00
Evan Cheng
c2084b74bb Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
llvm-svn: 96023
 2010-02-12 22:17:21 +00:00
Dale Johannesen
d52ea2ffc6 This should have gone in with 26015, see comments there. 
llvm-svn: 96020
 2010-02-12 22:00:40 +00:00
Johnny Chen
a56964de27 Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. 
llvm-svn: 96019
 2010-02-12 21:59:23 +00:00
Chris Lattner
2a0d9140f5 doxygenize some comments, patch by Peter Collingbourne! 
llvm-svn: 96018
 2010-02-12 21:54:28 +00:00
Dale Johannesen
ea96b2974f When save/restoring CR at prolog/epilog, in a large 
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.

llvm-svn: 96015
 2010-02-12 21:35:34 +00:00
Chris Lattner
2265d6280b Add support for a union type in LLVM IR. Patch by Talin! 
llvm-svn: 96011
 2010-02-12 20:49:41 +00:00
Johnny Chen
0f2837db87 Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. 
llvm-svn: 96010
 2010-02-12 20:48:24 +00:00
Evan Cheng
3e15f48df5 Also recognize armv6t2-* and armv5te-* triplets. 
llvm-svn: 96008
 2010-02-12 20:39:35 +00:00
Dan Gohman
cdb2e784ff Fix a case of mismatched types in an Add that turned up in 447.dealII. 
llvm-svn: 96007
 2010-02-12 20:39:25 +00:00
Evan Cheng
c75a237988 Add ARM bitcode file magic. 
llvm-svn: 96006
 2010-02-12 20:13:44 +00:00
Dan Gohman
cbf5771473 Reapply 95979, a compile-time speedup, now that the bug it exposed is fixed. 
llvm-svn: 96005
 2010-02-12 19:35:25 +00:00
Dan Gohman
006952d39d Fix this code to avoid dereferencing an end() iterator in 
offset distributions it doesn't expect.

llvm-svn: 96002
 2010-02-12 19:20:37 +00:00
Johnny Chen
473d813c5d Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. 
llvm-svn: 95999
 2010-02-12 18:55:33 +00:00
Dale Johannesen
c7b5b1dcfa Rewrite handling of DBG_VALUE; previous algorithm 
didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.

llvm-svn: 95996
 2010-02-12 18:40:17 +00:00
Chris Lattner
ecb203898a 1. modernize the constantmerge pass, using densemap/smallvector. 
2. don't bother trying to merge globals in non-default sections,
   doing so is quite dubious at best anyway.
3. fix a bug reported by Arnaud de Grandmaison where we'd try to
   merge two globals in different address spaces.

llvm-svn: 95995
 2010-02-12 18:17:23 +00:00
Chris Lattner
fbf6ef7c34 rename test 
llvm-svn: 95993
 2010-02-12 18:05:00 +00:00
Daniel Dunbar
43ad3dfe00 Revert "Reverse the order for collecting the parts of an addrec. The order", it 
is breaking llvm-gcc bootstrap.

llvm-svn: 95988
 2010-02-12 17:27:08 +00:00
Anton Korobeynikov
c66de6687b Testcases for recent stdcall / fastcall mangling improvements 
llvm-svn: 95982
 2010-02-12 15:29:13 +00:00
Anton Korobeynikov
ffbf0f7027 Setup correct data layout to match gcc's expectations on mingw32. 
llvm-svn: 95981
 2010-02-12 15:28:56 +00:00
Anton Korobeynikov
7073515c86 Cleanup stdcall / fastcall name mangling. 
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980
 2010-02-12 15:28:40 +00:00
Dan Gohman
2f46f79492 Reverse the order for collecting the parts of an addrec. The order 
doesn't matter, except that ScalarEvolution tends to need less time
to fold the results this way.

llvm-svn: 95979
 2010-02-12 11:08:26 +00:00
Dan Gohman
c40eb525ad Reapply the new LoopStrengthReduction code, with compile time and 
bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.

This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.

llvm-svn: 95975
 2010-02-12 10:34:29 +00:00
Lang Hames
46f6d32509 * Updated the cost matrix normalization proceedure to better handle infinite costs. 
* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.

llvm-svn: 95973
 2010-02-12 09:43:37 +00:00
Evan Cheng
dc2bb77b1b Update test to match 95961. 
llvm-svn: 95971
 2010-02-12 07:48:46 +00:00
Evan Cheng
06c22ed109 Test for 95961. 
llvm-svn: 95962
 2010-02-12 02:35:03 +00:00
Chris Lattner
c3dbd2e2fc add a bunch of mod/rm encoding types for fixed mod/rm bytes. 
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960
 2010-02-12 02:06:33 +00:00
Evan Cheng
86a3020e95 Test case for 95958. 
llvm-svn: 95959
 2010-02-12 02:02:23 +00:00
Chris Lattner
bde30aec54 revert r95949, it turns out that adding new prefixes is not a 
great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957
 2010-02-12 01:55:31 +00:00
Daniel Dunbar
08f1b2f670 MC: Fix bug where trailing tied operands were forgotten; the X86 assembler 
matcher is now free of implicit operands!
 - Still need to clean up the code now that we don't to worry about implicit
   operands, and to make it a hard error if an instruction fails to specify all
   of its operands for some reason.

llvm-svn: 95956
 2010-02-12 01:46:54 +00:00