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7380799e4a
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52219 Commits

Author SHA1 Message Date
Craig Topper
7380799e4a Truncate of undef is just undef of smaller size. 
llvm-svn: 148205
 2012-01-15 01:05:11 +00:00
Craig Topper
0c4ab86d2c Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. 
llvm-svn: 148196
 2012-01-14 18:29:57 +00:00
Craig Topper
ddc2e1091e Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions. 
llvm-svn: 148194
 2012-01-14 18:14:53 +00:00
Duncan Sands
96dee83647 Speculatively revert commit 148175 (rafael), to see if this fixes 
non-determinism in the 32 bit dragonegg buildbot.  Original commit
message:
Only emit the Leh_func_endN symbol when needed.

llvm-svn: 148191
 2012-01-14 17:16:48 +00:00
Andrew Trick
071cb0a076 Fix a corner case hit by redundant phi elimination running after LSR. 
Fixes PR11761: bad IR w/ redundant Phi elim

llvm-svn: 148177
 2012-01-14 03:17:23 +00:00
Rafael Espindola
a4e515db51 Only emit the Leh_func_endN symbol when needed. 
llvm-svn: 148175
 2012-01-14 02:36:51 +00:00
Andrew Trick
4bf8728f07 misched: Initial code for building an MI level scheduling DAG 
llvm-svn: 148174
 2012-01-14 02:17:18 +00:00
Andrew Trick
dcb9435036 Move physreg dependency generation into aptly named addPhysRegDeps. 
llvm-svn: 148173
 2012-01-14 02:17:15 +00:00
Andrew Trick
1fd0adb573 misched: Added ScheduleDAGInstrs::IsPostRA 
llvm-svn: 148172
 2012-01-14 02:17:12 +00:00
Andrew Trick
6b08526310 misched: Invoke the DAG builder on each sequence of schedulable instructions. 
llvm-svn: 148171
 2012-01-14 02:17:09 +00:00
Andrew Trick
ce507adb56 Move things around to make the file navigable, even though it will probably be split up later. 
llvm-svn: 148170
 2012-01-14 02:17:06 +00:00
Evan Cheng
c0e7b19ff0 After r147827 and r147902, it's now possible for unallocatable registers to be 
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
        cbnz    r6, LBB89_12
...
LBB89_12:
        ble     LBB89_1

The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.

rdar://10676853

llvm-svn: 148168
 2012-01-14 01:53:46 +00:00
Chad Rosier
4a705ae81a Fix pasto from r146196. 
llvm-svn: 148167
 2012-01-14 01:50:21 +00:00
Dan Gohman
4539e2a975 Fix an unused variable warning that Chad noticed. 
llvm-svn: 148164
 2012-01-14 00:47:44 +00:00
Rafael Espindola
2b55c13cf1 Remove previous commit while I debug the bot failures. 
llvm-svn: 148156
 2012-01-13 23:28:50 +00:00
Jakob Stoklund Olesen
b1f7df8d8b Use RegisterTuples to generate pseudo-registers. 
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.

This makes the call clobber lists longer, but I intend to get rid of
those soon.

llvm-svn: 148151
 2012-01-13 22:55:42 +00:00
Rafael Espindola
3a35eeb0aa Remove label that is not used anymore. 
llvm-svn: 148150
 2012-01-13 22:41:58 +00:00
Eli Friedman
a70048903b Speculatively revert r148132+r148133 to try and fix a buildbot failure. 
llvm-svn: 148149
 2012-01-13 22:34:39 +00:00
Andrew Trick
796cca6eff Remove pointless mode line in .cpp file. 
llvm-svn: 148143
 2012-01-13 22:04:16 +00:00
Devang Patel
410d6214f9 Revert r148131, it was committed before it was ready. 
llvm-svn: 148134
 2012-01-13 19:28:58 +00:00
Stepan Dyatkovskiy
81514d2471 Cosmetic patch for r148132. 
llvm-svn: 148133
 2012-01-13 19:27:22 +00:00
Stepan Dyatkovskiy
94682abb75 LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache). 
llvm-svn: 148132
 2012-01-13 19:13:54 +00:00
Devang Patel
194ad5ead8 Refactor. 
llvm-svn: 148131
 2012-01-13 19:12:18 +00:00
Craig Topper
c1e3d46e07 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. 
llvm-svn: 148112
 2012-01-13 09:21:41 +00:00
Craig Topper
e75115a861 use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1. 
llvm-svn: 148109
 2012-01-13 08:32:21 +00:00
Craig Topper
e52c0484de Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. 
llvm-svn: 148108
 2012-01-13 08:12:35 +00:00
Craig Topper
71ea42cc29 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. 
llvm-svn: 148106
 2012-01-13 06:59:47 +00:00
Andrew Trick
85c44d1485 Added the MachineSchedulerPass skeleton. 
llvm-svn: 148105
 2012-01-13 06:30:30 +00:00
Andrew Trick
97340838f5 wrong filename 
llvm-svn: 148103
 2012-01-13 06:30:22 +00:00
Andrew Trick
117f29f574 80-col violation 
llvm-svn: 148102
 2012-01-13 06:30:19 +00:00
Craig Topper
0e34a8e58c Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750. 
llvm-svn: 148101
 2012-01-13 06:12:41 +00:00
Craig Topper
32812741b7 Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. 
llvm-svn: 148096
 2012-01-13 05:04:25 +00:00
Jakob Stoklund Olesen
9ba097a208 Delete CodeInit and CodeRecTy from TableGen. 
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

llvm-svn: 148092
 2012-01-13 03:38:34 +00:00
Jakob Stoklund Olesen
3776477761 Use uniqued StringInit pointers for lookups. 
This avoids a gazillion StringMap and dynamic_cast calls, making
TableGen run 3x faster.

llvm-svn: 148091
 2012-01-13 03:16:35 +00:00
Evan Cheng
e31c929c2d DAGCombine's logic for forming pre- and post- indexed loads / stores were being 
overly conservative. It was concerned about cases where it would prohibit
folding simple [r, c] addressing modes. e.g.
  ldr r0, [r2]
  ldr r1, [r2, #4]
=>
  ldr r0, [r2], #4
  ldr r1, [r2]
Change the logic to look for such cases which allows it to form indexed memory
ops more aggressively.

rdar://10674430

llvm-svn: 148086
 2012-01-13 01:37:24 +00:00
Bill Wendling
c8f27fdf02 Fix off-by-one error. 
llvm-svn: 148077
 2012-01-13 00:41:53 +00:00
Dan Gohman
922244c634 Implement proper ObjC ARC objc_retainBlock "escape" analysis, so that 
the optimizer doesn't eliminate objc_retainBlock calls which are needed
for their side effect of copying blocks onto the heap.
This implements rdar://10361249.

llvm-svn: 148076
 2012-01-13 00:39:07 +00:00
Pete Cooper
f3141fef55 Added MVT::v2f16 
llvm-svn: 148067
 2012-01-12 23:14:13 +00:00
Bill Wendling
18abc22050 Revert accidental commit. 
llvm-svn: 148065
 2012-01-12 23:06:28 +00:00
Bill Wendling
ce528914e7 Fix the code that was WRONG. 
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.

llvm-svn: 148064
 2012-01-12 23:05:03 +00:00
Pete Cooper
1db82e3b84 Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to Promote for those operations. 
Sorry, no test case yet

llvm-svn: 148050
 2012-01-12 21:46:18 +00:00
Elena Demikhovsky
beb66de0f9 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.

llvm-svn: 148044
 2012-01-12 20:33:10 +00:00
Evan Cheng
4967772ebc When hoisting common code, watch out for uses which are marked "kill". If the 
killed registers are needed below the insertion point, then unset the kill
marker.

Sorry I'm not able to find a reduced test case.

rdar://10660944

llvm-svn: 148043
 2012-01-12 20:31:24 +00:00
Rafael Espindola
959adf57db Support segmented stacks on 64-bit FreeBSD. 
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.

llvm-svn: 148041
 2012-01-12 20:24:30 +00:00
Rafael Espindola
dda46f4081 Support segmented stacks on win32. 
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.

llvm-svn: 148040
 2012-01-12 20:22:08 +00:00
Evan Cheng
fc3ec91768 Allow targets to select source order pre-RA scheduler. 
llvm-svn: 148033
 2012-01-12 18:27:52 +00:00
Devang Patel
d568674834 Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.

llvm-svn: 148032
 2012-01-12 18:03:40 +00:00
Jakob Stoklund Olesen
73a72e7241 Make SplitAnalysis::UseSlots private. 
llvm-svn: 148031
 2012-01-12 17:53:44 +00:00
Benjamin Kramer
7678692172 After Jakob's r147938 exception handling on i386 was completely broken. 
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.

This should fix nightly tester failures.

llvm-svn: 148030
 2012-01-12 17:37:18 +00:00
Nadav Rotem
618722de09 Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors. 
The attached testcase was stuck in an endless loop.

llvm-svn: 148027
 2012-01-12 15:31:55 +00:00