Commit Graph

11556 Commits

Author SHA1 Message Date
Jim Grosbach
73ce6687df remove incorrect GCCBuiltin<> usage
llvm-svn: 104833
2010-05-27 15:04:02 +00:00
Gabor Greif
d8e3e9f572 typo
llvm-svn: 104832
2010-05-27 09:48:47 +00:00
Dan Gohman
0b5922b032 Fix Lint printing warnings multiple times. Remove the ErrorStr
option from lintModule, which was an artifact from being
based on Verifier code.

llvm-svn: 104765
2010-05-26 22:28:53 +00:00
Daniel Dunbar
bf243d9440 MC: Add TargetMachine support for setting the value of MCRelaxAll with
-filetype=obj.

llvm-svn: 104747
2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
1c0aa5f14a Add StringRef::compare_numeric and use it to sort TableGen register records.
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
2010-05-26 21:47:28 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
ISD::. No functional change.

llvm-svn: 104734
2010-05-26 20:22:18 +00:00
Bill Wendling
fbe85886bb Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
more than just the stack slot coloring algorithm.

llvm-svn: 104722
2010-05-26 19:46:12 +00:00
Dan Gohman
616845c384 Eliminate the use of PriorityQueue and just use a std::vector,
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718
2010-05-26 18:52:00 +00:00
Dan Gohman
3391366b42 Fix indentation.
llvm-svn: 104717
2010-05-26 18:37:48 +00:00
Daniel Dunbar
1b8e1aafae MC: Change RelaxInstruction to only take the input and output instructions.
llvm-svn: 104713
2010-05-26 18:15:06 +00:00
Daniel Dunbar
77240e2337 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
before encoding.

llvm-svn: 104707
2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
2010-05-26 17:27:12 +00:00
Daniel Dunbar
87dcbd1ee5 MC: Eliminate MCAsmFixup, replace with MCFixup.
llvm-svn: 104699
2010-05-26 15:18:56 +00:00
Daniel Dunbar
fe22195ea6 MC: Simplify MCFixup and increase the available offset size.
llvm-svn: 104698
2010-05-26 15:18:40 +00:00
Daniel Dunbar
55c1bf55fe MC: Use accessors for access to MCAsmFixup.
llvm-svn: 104697
2010-05-26 15:18:31 +00:00
Daniel Dunbar
a06aa279f4 MC: Eliminate MCFragment vtable, which was unnecessary.
llvm-svn: 104689
2010-05-26 06:50:57 +00:00
Eric Christopher
13ac28ede3 Temporarily revert r104655 as it's breaking the bots.
llvm-svn: 104664
2010-05-26 01:59:55 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.

llvm-svn: 104660
2010-05-26 01:21:14 +00:00
Dan Gohman
59cddd1327 Change push_all to a non-virtual function and implement it in the
base class, since all the implementations are the same.

llvm-svn: 104659
2010-05-26 01:10:55 +00:00
Dan Gohman
ba28c900a2 Delete an unused function.
llvm-svn: 104658
2010-05-26 00:56:27 +00:00
Bill Wendling
04fbdac5ac Dale and Evan suggested putting the "check for setjmp" much earlier in the
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
2010-05-26 00:28:19 +00:00
Eric Christopher
371732bd2a Start adding mach-o tls reloc support.
llvm-svn: 104651
2010-05-26 00:02:12 +00:00
Jakob Stoklund Olesen
41388819f1 Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
llvm-svn: 104650
2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
9210d3b189 Print symbolic SubRegIndex names on machine operands.
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
696fbed514 Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
2010-05-25 19:49:33 +00:00
Eric Christopher
627e887b3d Make sure aeskeygenassist uses an unsigned immediate field.
Fixes rdar://8017638

llvm-svn: 104617
2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
2010-05-24 21:46:58 +00:00
Evan Cheng
e34814c0bc Avoid adding duplicate function live-in's.
llvm-svn: 104560
2010-05-24 21:33:37 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
2010-05-24 14:48:12 +00:00
Daniel Dunbar
eb23d9ac22 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
llvm-svn: 104463
2010-05-23 17:44:06 +00:00
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
John Mosby
cec9b7fc9c Trivial change to dump() function for SparseBitVector
llvm-svn: 104433
2010-05-22 05:13:17 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977.
llvm-svn: 104421
2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
2010-05-22 01:06:18 +00:00
Eric Christopher
6bd67791da Add a new section and accessor for TLS data.
llvm-svn: 104411
2010-05-22 00:00:58 +00:00
Eric Christopher
0df4e8b6a5 Fix comment and whitespace.
llvm-svn: 104392
2010-05-21 22:39:11 +00:00
Evan Cheng
3c850aecf6 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
0f1087b284 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
2010-05-21 20:02:01 +00:00
Nathan Jeffords
28b485543b added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.

llvm-svn: 104334
2010-05-21 18:23:56 +00:00
Chris Lattner
1794093960 constify accessor.
llvm-svn: 104325
2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
a3cca88b41 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
edf8136011 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
6c22635216 If the first definition of a virtual register is a partial redef, add an
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
2010-05-21 16:32:16 +00:00
Matt Fleming
5d40d53cab Currently, createMachOStreamer() is invoked directly in llvm-mc which
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318
2010-05-21 12:54:43 +00:00
Matt Fleming
0ca99c0262 Add support for parsing the ELF .type assembler directive.
llvm-svn: 104316
2010-05-21 11:36:59 +00:00
Lang Hames
b579a16d82 Removed scaleNumbering method declaration from LiveInterval (not defined, not used).
llvm-svn: 104311
2010-05-21 03:04:04 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
llvm-svn: 104293
2010-05-20 23:26:43 +00:00
Devang Patel
3d4cd812aa Rename variable. add comment.
llvm-svn: 104274
2010-05-20 20:35:24 +00:00