86339 Commits

Author SHA1 Message Date
Sanjay Patel
76380d0013 remove outdated comment; NFC
llvm-svn: 258147
2016-01-19 17:29:22 +00:00
Eduard Burtescu
c55147fcdc [opaque pointer types] [NFC] GEP: replace get(Pointer)ElementType uses with get{Source,Result}ElementType.
Summary:
GEPOperator: provide getResultElementType alongside getSourceElementType.
This is made possible by adding a result element type field to GetElementPtrConstantExpr, which GetElementPtrInst already has.

GEP: replace get(Pointer)ElementType uses with get{Source,Result}ElementType.

Reviewers: mjacob, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D16275

llvm-svn: 258145
2016-01-19 17:28:00 +00:00
Michael Zuckerman
71a84dc5a5 [AVX512] Adding VPERMB instruction
Differential Revision: http://reviews.llvm.org/D16294

llvm-svn: 258144
2016-01-19 17:07:43 +00:00
Dan Gohman
fb437bc669 [WebAssembly] Rematerialize constants rather than hold them live in registers.
Teach the register stackifier to rematerialize constants that have multiple
uses instead of leaving them in registers. In the WebAssembly encoding, it's
the same code size to materialize most constants as it is to read a value
from a register.

llvm-svn: 258142
2016-01-19 16:59:23 +00:00
Rafael Espindola
2f2a76fc6a Simplify MCFillFragment.
The value size was always 1 or 0, so we don't need to store it.

In a no asserts build this takes the testcase of pr26208 from 11 to 10
seconds.

llvm-svn: 258141
2016-01-19 16:57:08 +00:00
Chad Rosier
a47859252e Typo.
llvm-svn: 258137
2016-01-19 16:50:45 +00:00
Marina Yatsina
adac739033 [X86] Add support for "xlat m8"
According to x86 spec "xlat m8" is a legal instruction and it is equivalent to "xlatb".

Differential Revision: http://reviews.llvm.org/D15150

llvm-svn: 258135
2016-01-19 16:35:38 +00:00
Manuel Jacob
a2e0ca38ae Fix constant folding of constant vector GEPs with undef or null as pointer argument.
Reviewers: eddyb

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D16321

llvm-svn: 258134
2016-01-19 16:34:31 +00:00
Marina Yatsina
d7dac8fde4 [X86] Adding support for missing variations of X86 string related instructions
The following are legal according to X86 spec:
ins mem, DX
outs DX, mem
lods mem
stos mem
scas mem
cmps mem, mem
movs mem, mem

Differential Revision: http://reviews.llvm.org/D14827

llvm-svn: 258132
2016-01-19 15:37:56 +00:00
Manuel Jacob
eacda01c05 Rename Variable Ptr to PtrTy. NFC.
llvm-svn: 258130
2016-01-19 15:21:15 +00:00
Rafael Espindola
b750d2d403 Handle 64 bit offsets.
No tests since llvm-mc takes 14 seconds on it. I will try to improve it
and then test.

Part of pr26208.

llvm-svn: 258129
2016-01-19 15:19:08 +00:00
Dan Gohman
d5444c8fc8 [WebAssembly] Disable some WebAssembly-specific optimization passes at -O0.
llvm-svn: 258127
2016-01-19 14:55:02 +00:00
Dan Gohman
5556fe04f3 [WebAssembly] Use the templated form of MachineFunction::getSubtarget(). NFC.
llvm-svn: 258126
2016-01-19 14:53:19 +00:00
Dan Gohman
e8c29f17af [WebAssembly] Re-enable loop idiom recognition for memcpy et al.
llvm-svn: 258125
2016-01-19 14:49:23 +00:00
Asaf Badouh
19e99238a0 [X86][AVX512]fix dag & add intrinsics for fixupimm
cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics

Differential Revision: http://reviews.llvm.org/D16313

llvm-svn: 258124
2016-01-19 14:21:39 +00:00
Philip Reames
4a8129f191 [GC] Lower vectors-of-pointers directly by default
This commit changes the default on our lowering of vectors-of-pointers from splitting in RS4GC to reporting them in the final stack map.  All of the changes to do so are already in place and tested.  Assuming no problems are unearthed in the next week, we will be deleting the old code entirely next Monday.

llvm-svn: 258111
2016-01-19 04:18:24 +00:00
Philip Reames
d600d56e01 [GC] Consolidate all built in GCs into a single file [NFC]
Combine a bunch of small files into a single, still rather small, file.  The primary purpose of this is to get all of the static initializers into a single file so as to have a well defined order of initialization.  

llvm-svn: 258109
2016-01-19 03:57:18 +00:00
Kelvin Li
67f0e62e45 parseArch() supports more variations of arch names for PowerPC builds
llvm-svn: 258103
2016-01-19 00:04:41 +00:00
Tobias Edler von Koch
ef41afb1e8 Add a change accidentally left out from r258100
Also remove an executable bit introduced by r258083.

llvm-svn: 258101
2016-01-18 23:35:24 +00:00
Tobias Edler von Koch
c19c96e06f [LTO] Restore original linkage of externals prior to splitting
Summary:
This is a companion patch for http://reviews.llvm.org/D16124.

Internalized symbols increase the size of strongly-connected components in
SCC-based module splitting and thus reduce the amount of parallelism. This
patch records the original linkage of non-local symbols prior to
internalization and then restores it just before splitting/CodeGen. This is
also useful for cases where the linker requires symbols to remain external, for
instance, so they can be placed according to linker script rules.

It's currently under its own flag (-restore-globals) but should eventually
share a common flag with D16124.

Reviewers: joker.eph, pcc

Subscribers: slarin, llvm-commits, joker.eph

Differential Revision: http://reviews.llvm.org/D16229

llvm-svn: 258100
2016-01-18 23:24:54 +00:00
Simon Pilgrim
82a3dcbbfd Fixed MSVC warning that not all control paths return a value.
llvm-svn: 258099
2016-01-18 22:54:46 +00:00
Matt Arsenault
348623d27f AMDGPU: Reduce 64-bit SRAs
llvm-svn: 258096
2016-01-18 22:09:04 +00:00
Matt Arsenault
862bf93c73 AMDGPU: Split 64-bit and of constant up
This breaks the tests that were meant for testing
64-bit inline immediates, so move those to shl where
they won't be broken up.

This should be repeated for the other related bit ops.

llvm-svn: 258095
2016-01-18 22:01:13 +00:00
Chad Rosier
8c72479955 [AArch64] Remove unused arguments. NFC.
AFAICT, these have been unused since the initial backend import.

llvm-svn: 258093
2016-01-18 21:56:40 +00:00
Matt Arsenault
97aeb607e4 AMDGPU: Generalize shl combine
Reduce 64-bit shl with constant > 32. We already special cased
this for the == 32 case, but this also works for any >= 32 constant.

llvm-svn: 258092
2016-01-18 21:55:14 +00:00
Matt Arsenault
e1a6e6ae7f AMDGPU: Reduce 64-bit lshr by constant to 32-bit
64-bit shifts are very slow on some subtargets.

llvm-svn: 258090
2016-01-18 21:43:36 +00:00
Adam Nemet
0049eafd88 [LAA] Include function name in debug output
llvm-svn: 258088
2016-01-18 21:16:33 +00:00
Matt Arsenault
1478312f09 AMDGPU: Add subtarget feature for instruction rates
llvm-svn: 258085
2016-01-18 21:13:50 +00:00
Simon Pilgrim
269ccdb97d Fixed MSVC Win64 warning of implicit conversion of 32-bit shift to 64-bits.
llvm-svn: 258084
2016-01-18 21:11:19 +00:00
Sergei Larin
72115d5fb6 Add to the split module utility an SCC based method which allows not to globalize any local variables.
Summary:
    Currently llvm::SplitModule as the first step globalizes all local objects, which might not be desirable in some scenarios.
    This change adds a new flag to llvm::SplitModule that uses SCC approach to search for a balanced partition without the need to externalize symbols.
    Such partition might not be possible or fully balanced for a given number of partitions, and is a function of the module properties (global/local dependencies within the module).
    
    Joint development Tobias Edler von Koch (tobias@codeaurora.org) and Sergei Larin (slarin@codeaurora.org)
    
    Subscribers: llvm-commits, joker.eph
    
    Differential Revision: http://reviews.llvm.org/D16124

llvm-svn: 258083
2016-01-18 21:07:13 +00:00
Simon Pilgrim
4c1241282f [X86][AVX2] Broadcast subvectors
AVX2 can only broadcast from the zero'th element of a vector, but if the broadcastable element is the zero'th element of a 128-bit subvector its advantageous to extract the subvector, broadcast from that and avoid the loading of shuffle mask data that would be needed for VPERMPS/VPERMD. The only exception being when the source type is 4f64 or 4i64 which can directly use the immediate shuffle VPERMPD/VPERMQ directly.

Differential Revision: http://reviews.llvm.org/D16050

llvm-svn: 258081
2016-01-18 20:59:04 +00:00
Krzysztof Parzyszek
c8377aa82b [Hexagon] Recognize more copy-equivalents in RDF optimizations
llvm-svn: 258076
2016-01-18 20:45:51 +00:00
Krzysztof Parzyszek
7ff439af60 [RDF] Improvements to copy propagation
- Allow any instruction to define equality between registers.
- Keep the DFG updated.

llvm-svn: 258075
2016-01-18 20:43:57 +00:00
Krzysztof Parzyszek
fa20b3ad96 [RDF] Improve compile-time performance of dead code elimination
llvm-svn: 258074
2016-01-18 20:42:47 +00:00
Krzysztof Parzyszek
a9c1a4bbfd [RDF] Allow unlinking ref nodes from data-flow chains only
llvm-svn: 258073
2016-01-18 20:41:34 +00:00
Craig Topper
7b0b0f6cca [TableGen] Use FoldingSets instead of DenseMaps to unique UnOpInit, BinOpInit and TernOpInit. This remove the memory needed to store the key for the DenseMap. NFC
llvm-svn: 258071
2016-01-18 20:36:06 +00:00
Craig Topper
4b8a0e95c4 [TableGen] Fix an assert I missed in r258063.
llvm-svn: 258068
2016-01-18 19:59:05 +00:00
Tom Stellard
a09c2fcc35 TargetLowering: Improve handling of (setcc ([sz]ext x) 0, cc) in SimplifySetCC
Summary:
When SimplifySetCC sees a setcc node that compares the result of a
value extension operation with a constant, it tries to simplify the
setcc node by eliminating the extension and shrinking the constant.

If shrinking the inputs to setcc is deemed not desirable by the target
(e.g. the target does not want a setcc comparing i1 values), then it
is still possible to optimize this sequence in some cases.

This patch adds the following combines to SimplifySetCC when shrinking setcc
inputs is not desirable:

(setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> (setcc (x, y, cc))
(setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> (setcc (x, Y, !cc))

There are no tests for this yet, but once AMDGPU correctly implements
TargetLowering::isTypeDesirableForOp(), this new combine will be
exercised by the existing CodeGen/AMDGPU/setcc-opt.ll test.

Reviewers: resistor, arsenm

Subscribers: jroelofs, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15034

llvm-svn: 258067
2016-01-18 19:55:21 +00:00
Craig Topper
a5ac333af9 [TableGen] Merge the SuperClass Record and SMRange vector into a single vector. This removes the state needed to manage the extra vector thus reducing the size of the Record class. NFC
llvm-svn: 258065
2016-01-18 19:52:37 +00:00
Craig Topper
22fa1c4ac6 [TableGen] Allocate the Init pointer array for BitsInit/ListInit after the BitsInit/ListInit object itself. Saves a bit of memory. NFC
llvm-svn: 258063
2016-01-18 19:52:24 +00:00
Sanjay Patel
5b6411a86b combine clauses with same output ; NFCI
llvm-svn: 258062
2016-01-18 19:17:58 +00:00
Sanjay Patel
4f9ef4b7f0 use m_OneUse ; NFCI
llvm-svn: 258059
2016-01-18 18:36:38 +00:00
Sanjay Patel
08bcf5f0bd fix variable names, typos ; NFC
llvm-svn: 258058
2016-01-18 18:28:09 +00:00
Sanjay Patel
5dcccbe4e7 fix typo; NFC
llvm-svn: 258057
2016-01-18 17:50:23 +00:00
Igor Breger
7327a3bf3b AVX512: Masked store intrinsic implementation.
Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.

Differential Revision: http://reviews.llvm.org/D16271

llvm-svn: 258047
2016-01-18 13:52:57 +00:00
Elena Demikhovsky
0090e74974 Added Cannonlake processor to X86 Target
Differential Revision: http://reviews.llvm.org/D16289

llvm-svn: 258046
2016-01-18 13:00:31 +00:00
Igor Breger
74d74d20c2 AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl instruction.
code example , previous implementation.
    movzbl  %dil, %eax
    kmovw  %eax, %k0
  new code
    kmovw  %edi, %k0

Differential Revision: http://reviews.llvm.org/D16287

llvm-svn: 258045
2016-01-18 12:02:45 +00:00
Oliver Stannard
ec1b7475d8 [ARM] Operands for PKHTB alias should be swapped
When the shift immediate is zero, PKHTB is an alias for PKHBT, but the order of
the input operands needs to be swapped.

Differential Revision: http://reviews.llvm.org/D16288

llvm-svn: 258044
2016-01-18 11:56:35 +00:00
Michael Zuckerman
b0cb95e40b [AVX512] adding AVXVBMI feature flag
Fixing wrong typo (avx515) → (avx512) 
Review over the shoulder by asaf . 

Differential Revision: http://reviews.llvm.org/D16190

llvm-svn: 258041
2016-01-18 11:12:47 +00:00
Xinliang David Li
7d5bc597d7 [Coverage] move a local var to be BinaryCoverageReader's member
The symtab is logically referenced beyond the call to the create
method. This changes makes sure its lifetime matches that of
the reader.

llvm-svn: 258036
2016-01-18 06:48:01 +00:00