139272 Commits

Author SHA1 Message Date
Kostya Serebryany
77bcf6126c [libFuzzer] refactoring to speed things up, NFC
llvm-svn: 283946
2016-10-11 21:27:37 +00:00
Reid Kleckner
f071744d81 Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues"
Reverts r283938 to reinstate r283867 with a fix.

The original change had an ArrayRef referring to a destroyed temporary
initializer list. Use plain C arrays instead.

llvm-svn: 283942
2016-10-11 21:14:03 +00:00
Kevin Enderby
78b9ef248b Next set of additional error checks for invalid Mach-O files for the
load commands that uses the MachO::linker_option_command
type but not used in llvm libObject code but used in llvm tool code.

This includes just LC_LINKER_OPTION load command.

llvm-svn: 283939
2016-10-11 21:04:39 +00:00
Reid Kleckner
a5f5d77747 Revert "[Thumb] Save/restore high registers in Thumb1 pro/epilogues"
This reverts r283867.

This appears to be an infinite loop:

    while (HiRegToSave != AllHighRegs.end() && CopyReg != AllCopyRegs.end()) {
      if (HiRegsToSave.count(*HiRegToSave)) {
        ...

        CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegs.end());
        HiRegToSave =
            findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegs.end());
      }
    }

llvm-svn: 283938
2016-10-11 20:54:41 +00:00
Tim Northover
f238c4b92c GlobalISel: support selection of extend operations.
Patch mostly by Ahmed Bougaca.

llvm-svn: 283937
2016-10-11 20:50:21 +00:00
Tim Northover
573697e8ef MIRParser: allow types on registers with a RegBank.
This fixes some GlobalISel regression tests.

llvm-svn: 283936
2016-10-11 20:50:04 +00:00
Jordan Rose
201cd0c255 Re-apply "Disallow ArrayRef assignment from temporaries."
This re-applies r283798, disabled in r283803, with the static_assert
tests disabled under MSVC. The deleted functions still seem to catch
mistakes in MSVC, so it's not a significant loss.

Part of rdar://problem/16375365

llvm-svn: 283935
2016-10-11 20:39:16 +00:00
Kyle Butt
abb4b9d9ee Codegen: Tail-duplicate during placement.
The tail duplication pass uses an assumed layout when making duplication
decisions. This is fine, but passes up duplication opportunities that
may arise when blocks are outlined. Because we want the updated CFG to
affect subsequent placement decisions, this change must occur during
placement.

In order to achieve this goal, TailDuplicationPass is split into a
utility class, TailDuplicator, and the pass itself. The pass delegates
nearly everything to the TailDuplicator object, except for looping over
the blocks in a function. This allows the same code to be used for tail
duplication in both places.

This change, in concert with outlining optional branches, allows
triangle shaped code to perform much better, esepecially when the
taken/untaken branches are correlated, as it creates a second spine when
the tests are small enough.

Issue from previous rollback fixed, and a new test was added for that
case as well. Issue was worklist/scheduling/taildup issue in layout.

Issue from 2nd rollback fixed, with 2 additional tests. Issue was
tail merging/loop info/tail-duplication causing issue with loops that share
a header block.

Issue with early tail-duplication of blocks that branch to a fallthrough
predecessor fixed with test case: tail-dup-branch-to-fallthrough.ll

Differential revision: https://reviews.llvm.org/D18226

llvm-svn: 283934
2016-10-11 20:36:43 +00:00
Sanjay Patel
0a908a5fae [x86] add tests for negate bool
llvm-svn: 283930
2016-10-11 20:15:20 +00:00
Reid Kleckner
01e7d754c4 Avoid braced initialization for default member initializers for MSVC 2013
llvm-svn: 283928
2016-10-11 20:02:57 +00:00
Arnold Schwaighofer
7430f50b4d Silence -Wunused-but-set-variable warning
llvm-svn: 283927
2016-10-11 19:49:29 +00:00
Rui Ueyama
35bd62db88 Re-submit r283823: Define DbiStreamBuilder::addDbgStream to add stream.
The previous commit was failing because we filled empty slots of
the debug stream index with kInvalidStreamIndex. It should've been 0.

llvm-svn: 283925
2016-10-11 19:43:12 +00:00
Kostya Serebryany
cb7566ce29 [sanitizer-coverage] use private linkage for coverage guards, delete old commented-out code.
llvm-svn: 283924
2016-10-11 19:36:50 +00:00
Rui Ueyama
7d7380c0c5 Fix build error on LP64 platforms.
llvm-svn: 283922
2016-10-11 19:28:56 +00:00
Zachary Turner
75f19d6b26 [raw_ostream] Raise some helper functions out of raw_ostream.
Low level functionality to format numbers were embedded in the
implementation of raw_ostream.  I have need to use these through
an interface other than the overloaded stream operators, so they
need to be raised to a level that they can be used from either
raw_ostream operators or other code.

llvm-svn: 283921
2016-10-11 19:24:45 +00:00
Konstantin Zhuravlyov
277eacdebe [AMDGPU] Refactor waitcnt encoding
- Refactor bit packing/unpacking
- Calculate bit mask given bit shift and bit width
- Introduce function for decoding bits of waitcnt
- Introduce function for encoding bits of waitcnt
- Introduce function for getting waitcnt mask (instead of using bare numbers)
- Introduce function fot getting max waitcnt(s) (instead of using bare numbers)

Differential Revision: https://reviews.llvm.org/D25298

llvm-svn: 283919
2016-10-11 18:58:22 +00:00
Dehao Chen
216f4733f3 Allow Switch instruction to have extractProfTotalWeight called as it can terminate a basic block. (NFC)
llvm-svn: 283918
2016-10-11 18:53:00 +00:00
Reid Kleckner
356339ee08 Avoid unnecessary constexpr to appease MSVC 2013
llvm-svn: 283916
2016-10-11 18:35:13 +00:00
Mehdi Amini
93003b9ee7 Fix "static initialization order fiasco" for the XCore Target.
I fixed all the other Targets in r283702, and interestingly the
sanitizers are only now "sometimes" catching this bug on the only
one I missed.

llvm-svn: 283914
2016-10-11 18:22:41 +00:00
Zachary Turner
df03c05965 [Support] Fix undefined behavior in RandomNumberGenerator.
This has existed pretty much forever AFAICT, but the code was
never being exercised because nobody was using the class.  A
user of this class surfaced, and now we're breaking with UB.
The code was obviously wrong, so it's fixed here.

llvm-svn: 283912
2016-10-11 18:17:26 +00:00
Konstantin Zhuravlyov
17d3d074b0 [AMDGPU] Fix test that was broken by rL283893
llvm-svn: 283911
2016-10-11 18:16:56 +00:00
NAKAMURA Takumi
9ce6934080 ARMMachineFunctionInfo.cpp: Add an initializer of ARMFunctionInfo::ReturnRegsCount in the explicit ctor.
It caused crash since r283867.

llvm-svn: 283909
2016-10-11 17:38:30 +00:00
NAKAMURA Takumi
f500124315 Reformat.
llvm-svn: 283908
2016-10-11 17:38:25 +00:00
Sanjay Patel
237ffdc433 [DAG] add fold for masked negated sign-extended bool
This enhances the fold added with:
https://reviews.llvm.org/rL283900

llvm-svn: 283905
2016-10-11 17:05:52 +00:00
Sanjay Patel
bfa7bcc6bc [x86] add sext variants of tests added with r283894
llvm-svn: 283903
2016-10-11 16:49:52 +00:00
Bernard Ogden
cc2f9f7cc0 Let test pass for builds that support X86, but do not default to it
Differential Revision: https://reviews.llvm.org/D25471

llvm-svn: 283902
2016-10-11 16:34:49 +00:00
Bernard Ogden
3ad1eb5426 Fix test on non-x86 hosts
Summary:
This test is allowed to run on non-x86 hosts and thus must use
llvm-nm rather than nm.

Differential Revision: https://reviews.llvm.org/D25473

llvm-svn: 283901
2016-10-11 16:32:37 +00:00
Sanjay Patel
61a6f1d61e [DAG] add fold for masked negated extended bool
The non-obvious motivation for adding this fold (which already happens in InstCombine)
is that we want to canonicalize IR towards select instructions and canonicalize DAG 
nodes towards boolean math. So we need to recreate some folds in the DAG to handle that
change in direction. 

An interesting implementation difference for cases like this is that InstCombine
generally works top-down while the DAG goes bottom-up. That means we need to detect 
different patterns. In this case, the SimplifyDemandedBits fold prevents us from 
performing a zext to sext fold that would then be recognized as a negation of a sext. 

llvm-svn: 283900
2016-10-11 16:26:36 +00:00
Daniel Jasper
9861a3ad52 Silence unused warning in non-assert builds.
llvm-svn: 283899
2016-10-11 16:22:36 +00:00
Adam Nemet
1b02274c11 [opt-viewer] Remove unnecessary call to demangle
llvm-svn: 283898
2016-10-11 16:20:40 +00:00
Adam Nemet
ee4aced190 [opt-viewer] Print hotness as percentage of the maximum hotness
llvm-svn: 283897
2016-10-11 16:20:38 +00:00
Adam Nemet
27f691d520 [opt-viewer] Convert another HTML output to use a multiline string
llvm-svn: 283896
2016-10-11 16:19:06 +00:00
Sanjay Patel
b056d8af79 [x86] add tests to show missed folds for masked bools
llvm-svn: 283894
2016-10-11 16:04:37 +00:00
Changpeng Fang
1632d75b59 AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11.
Differential Revision:
  http://reviews.llvm.org/D25454

Reviewers:
  tstellarAMD

llvm-svn: 283893
2016-10-11 16:00:47 +00:00
Zachary Turner
a08a487ce3 [cl] Don't print subcommand help when no subcommands present.
Previously we would print

  USAGE: <exe> [subcommand] [options]

Even if no subcommands were present.  This changes the output
format to only print "[subcommand]" if there is at least one
subcommand.

Fixes llvm.org/pr30598

Patch by Serge Guelton

llvm-svn: 283892
2016-10-11 15:58:48 +00:00
Sanjay Patel
dc0ba19eca [DAG] simplify logic; NFC
llvm-svn: 283885
2016-10-11 14:14:30 +00:00
Sanjay Patel
fbe8e33811 [DAG] hoist DL(N) and fix formatting; NFC
llvm-svn: 283884
2016-10-11 14:04:24 +00:00
Simon Pilgrim
7634f30e49 [X86][SSE] Regenerate scalar i64 uitofp test
Added 32-bit target test

llvm-svn: 283883
2016-10-11 14:01:38 +00:00
Simon Pilgrim
cc850df16d [X86][SSE] Regenerate vector load-trunc test
llvm-svn: 283881
2016-10-11 13:55:49 +00:00
Simon Pilgrim
e5236e5c4f [X86][SSE] Regenerate vsplit and tests
To make it more obvious how bad some of that truncation code is....

llvm-svn: 283880
2016-10-11 13:51:44 +00:00
Sanjay Patel
edf39dd95a [DAG] fix formatting; NFC
llvm-svn: 283878
2016-10-11 13:47:43 +00:00
Igor Laevsky
8051eefbd0 [LCSSA] Implement linear algorithm for the isRecursivelyLCSSAForm
For each block check that it doesn't have any uses outside of it's innermost loop.

Differential Revision: https://reviews.llvm.org/D25364

llvm-svn: 283877
2016-10-11 13:37:22 +00:00
Sanjay Patel
b7e522ea45 [x86] update test to use FileCheck and auto-generate checks
llvm-svn: 283876
2016-10-11 13:36:07 +00:00
George Rimar
9b695d5438 [Support/ELF] - Add OpenBSD PT_OPENBSD_RANDOMIZE, PT_OPENBSD_WXNEEDED constants.
Docs for reference:
http://man.openbsd.org/OpenBSD-current/man5/elf.5
2a5a8fc7e3

llvm-svn: 283872
2016-10-11 11:53:33 +00:00
Oliver Stannard
282bb1aaf0 [Thumb] Save/restore high registers in Thumb1 pro/epilogues
The high registers are not allocatable in Thumb1 functions, but they
could still be used by inline assembly, so we need to save and restore
the callee-saved high registers (r8-r11) in the prologue and epilogue.

This is complicated by the fact that the Thumb1 push and pop
instructions cannot access these registers. Therefore, we have to move
them down into low registers before pushing, and move them back after
popping into low registers.

In most functions, we will have low registers that are also being
pushed/popped, which we can use as the temporary registers for
saving/restoring the high registers. However, this is not guaranteed, so
we may need to push some extra low registers to ensure that the high
registers can be saved/restored. For correctness, it would be sufficient
to use just one low register, but if we have enough low registers
available then we only need one push/pop instruction, rather than one
per high register.

We can also use the argument/return registers when they are not live,
and the link register when saving (but not restoring), reducing the
number of extra registers we need to push.

There are still a few extreme edge cases where we need two push/pop
instructions, because not enough low registers can be made live in the
prologue or epilogue.

In addition to the regression tests included here, I've also tested this
using a script to generate functions which clobber different
combinations of registers, have different numbers of argument and return
registers (including variadic arguments), allocate different fixed sized
objects on the stack, and do or don't use variable sized allocas and the
__builtin_return_address intrinsic (all of which affect the available
registers in the prologue and epilogue). I ran these functions in a test
harness which verifies that all of the callee-saved registers are
correctly preserved.

Differential Revision: https://reviews.llvm.org/D24228

llvm-svn: 283867
2016-10-11 10:12:25 +00:00
Oliver Stannard
674ab91499 [ARM] Fix registers clobbered by SjLj EH on soft-float targets
Currently, the Int_eh_sjlj_dispatchsetup intrinsic is marked as
clobbering all registers, including floating-point registers that may
not be present on the target. This is technically true, as we could get
linked against code that does use the FP registers, but that will not
actually work, as the soft-float code cannot save and restore the FP
registers. SjLj exception handling can only work correctly if either all
or none of the code is built for a target with FP registers. Therefore,
we can assume that, when Int_eh_sjlj_dispatchsetup is compiled for a
soft-float target, it is only going to be linked against other
soft-float code, and so only clobbers the general-purpose registers.
This allows us to check that no non-savable registers are clobbered when
generating the prologue/epilogue.

Differential Revision: https://reviews.llvm.org/D25180

llvm-svn: 283866
2016-10-11 10:06:59 +00:00
Diana Picus
aa4f835b48 [AArch64] Allow label arithmetic with add/sub/cmp
Allow instructions such as 'cmp w0, #(end - start)' by folding the
expression into a constant. For ELF, we fold only if the symbols are in
the same section. For MachO, we fold if the expression contains only
symbols that are not linker visible.

Fixes https://llvm.org/bugs/show_bug.cgi?id=18920

Differential Revision: https://reviews.llvm.org/D23834

llvm-svn: 283862
2016-10-11 09:17:47 +00:00
Fraser Cormack
33445c78d3 Fix formatting in findRegisterUseOperandIdx. NFC.
llvm-svn: 283860
2016-10-11 09:09:21 +00:00
George Rimar
6b40301d99 Reverted r283740 [Object/ELF] - Do not crash on invalid Header->e_shoff value.
Bot does not like it: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/17075

/mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/test/Object/invalid.test:70:32: error: expected string not found in input
INVALID-SEC-ADDRESS-ALIGNMENT: Invalid address alignment of section headers
                               ^
<stdin>:1:1: note: scanning from here
/mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Object/ELF.h:412:7: runtime error: upcast of misaligned address 0x000002d8b899 for type 'llvm::object::Elf_Shdr_Impl<llvm::object::ELFType<llvm::support::endianness::little, true> >', which requires 2 byte alignment
^
<stdin>:1:125: note: possible intended match here
/mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Object/ELF.h:412:7: runtime error: upcast of misaligned address 0x000002d8b899 for type 'llvm::object::Elf_Shdr_Impl<llvm::object::ELFType<llvm::support::endianness::little, true> >', which requires 2 byte alignment
          

llvm-svn: 283858
2016-10-11 08:12:27 +00:00
Daniel Jasper
80e95dce89 Revert "Codegen: Tail-duplicate during placement."
This reverts commit r283842.

test/CodeGen/X86/tail-dup-repeat.ll causes and llc crash with our
internal testing. I'll share a link with you.

llvm-svn: 283857
2016-10-11 07:36:11 +00:00