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1500 Commits

Author SHA1 Message Date
Mikhail Glushenkov
cf04ed88af Move llvmc2 header files under include/llvm/CompilerDriver 
llvm-svn: 56466
 2008-09-22 20:50:40 +00:00
Mikhail Glushenkov
3895eee874 Plugin support for llvmc2 (a-la opt). 
llvm-svn: 56465
 2008-09-22 20:49:34 +00:00
Mikhail Glushenkov
e412a69526 Make comments a little bit more clear. 
llvm-svn: 56463
 2008-09-22 20:48:22 +00:00
Mikhail Glushenkov
72e4c4e976 Get rid of GlobalLanguageMap. Global state is evil. 
llvm-svn: 56462
 2008-09-22 20:47:46 +00:00
Mikhail Glushenkov
7afbd753b7 Add a (forward_as) option property 
llvm-svn: 56459
 2008-09-22 20:46:19 +00:00
Mikhail Glushenkov
54297e6546 Delete the file llvmc2/doc/LLVMC-Enhancements.rst + some minor language/spelling fixes. 
llvm-svn: 56458
 2008-09-22 20:45:17 +00:00
Oscar Fuentes
0f25988689 Initial support for the CMake build system. 
llvm-svn: 56419
 2008-09-22 01:08:49 +00:00
Evan Cheng
b3923fd86f Add instruction names as comments to InstBits entries. 
llvm-svn: 56275
 2008-09-17 06:29:52 +00:00
Devang Patel
7267b480ef Remove. 
llvm-svn: 56256
 2008-09-16 22:26:44 +00:00
Bill Wendling
932818c75a Reverting r56249. On further investigation, this functionality isn't needed. 
Apologies for the thrashing.

llvm-svn: 56251
 2008-09-16 21:48:12 +00:00
Bill Wendling
1a240c8033 - Change "ExternalSymbolSDNode" to "SymbolSDNode". 
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
 2008-09-16 21:12:30 +00:00
Devang Patel
b980f023ca Extract optimization pass selection code from llvm-gcc into a separate routine. 
This can be used by other stand alone tools, such as 'opt'.

llvm-svn: 56229
 2008-09-15 21:13:42 +00:00
Dan Gohman
cfe792b491 Update the LLVM polygen grammar for recent language changes: 
x86_ssecallcc, function notes, and some whitespace adjustments.

llvm-svn: 56221
 2008-09-15 16:10:51 +00:00
Dan Gohman
082879cfde Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and 
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162
 2008-09-12 18:08:03 +00:00
Dan Gohman
89660301e3 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
 2008-09-12 16:56:44 +00:00
Evan Cheng
2d51d1299e Indentation. 
llvm-svn: 56107
 2008-09-11 17:31:12 +00:00
Jim Grosbach
f53af44e09 lib/Target/SubtargetFeature.cpp asserts that the FeatureKV[] table be sorted 
by its first field, but TableGen doesn't actually enforce creating it that 
way. TableGen sorts the records that will be used to create it by the names 
of the records, not the Name field of those records.

This patch corrects the sort to use the "Name" field of the record as the 
sort key.

llvm-svn: 56106
 2008-09-11 17:05:32 +00:00
Evan Cheng
aebadcd733 Change getSubReg semantics. It now returns zero if the specified register doesn't have a subreg of the specified index. 
llvm-svn: 56099
 2008-09-11 06:25:25 +00:00
Dan Gohman
84924c9ceb Fix typos in (generated) comments. 
llvm-svn: 55916
 2008-09-08 16:29:36 +00:00
Evan Cheng
f8d8287454 Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs. 
llvm-svn: 55893
 2008-09-08 08:39:33 +00:00
Evan Cheng
8f1ac64bc9 Eliminate a compile time warning. 
llvm-svn: 55878
 2008-09-07 09:00:57 +00:00
Evan Cheng
018d570cb8 Fix indentation of generated code. 
llvm-svn: 55876
 2008-09-07 08:23:06 +00:00
Evan Cheng
4fb8cbebe4 Ignore multi-instruction patterns. e.g. 
def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

llvm-svn: 55875
 2008-09-07 08:19:51 +00:00
Evan Cheng
43c7084625 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
llvm-svn: 55679
 2008-09-03 00:03:49 +00:00
Evan Cheng
9817be2f96 Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes. 
llvm-svn: 55623
 2008-09-02 06:51:36 +00:00
Owen Anderson
3aa3841da2 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Dan Gohman
c7b8401b77 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00
Gabor Greif
de8ed9f431 just a brain dump for a small tool 
that brings us to 80-col violations
or tabs.

Usage:
  visit-violations <file>

At the moment it outputs editor invocations.

llvm-svn: 55509
 2008-08-28 23:15:28 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
llvm-svn: 55504
 2008-08-28 21:40:38 +00:00
Owen Anderson
a5b87bf7e2 Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling. 
llvm-svn: 55480
 2008-08-28 18:06:12 +00:00
Dan Gohman
378f477a02 Update a comment to reflect recent changes. 
llvm-svn: 55418
 2008-08-27 16:18:22 +00:00
Dan Gohman
5e5f1c9e8f Basic FastISel support for floating-point constants. 
llvm-svn: 55401
 2008-08-27 01:09:54 +00:00
Gabor Greif
4b86114f92 disallow direct access to SDValue::ResNo, provide a getter instead 
llvm-svn: 55394
 2008-08-26 22:36:50 +00:00
Dan Gohman
84d7f86244 Refactor a bunch of FastISelEmitter code into a helper class, and 
put each major step in a separate function. This makes the high
level sequence of events easier to follow.

llvm-svn: 55385
 2008-08-26 21:21:20 +00:00
Cedric Venet
62a65ed510 - small bug corrected: incorrect iterator type. 
- fix to please VS: add a return after an assert.

llvm-svn: 55380
 2008-08-26 19:49:04 +00:00
Owen Anderson
9e2381b77d We need to check that the return type is correct, even in cases where we don't 
have a return type that differs from the operand types.

llvm-svn: 55376
 2008-08-26 18:50:00 +00:00
Chris Lattner
1804f18b34 code simplification, no functionality change. 
llvm-svn: 55363
 2008-08-26 07:01:28 +00:00
Chris Lattner
006fc6636d stabilize more printing, this doesn't cause a problem 
in the example attached to PR2590, but is a problem in general.

llvm-svn: 55361
 2008-08-26 06:50:46 +00:00
Chris Lattner
6adb1b1b26 stablize SubRegsSet printing, part of PR2590 
llvm-svn: 55360
 2008-08-26 06:49:06 +00:00
Chris Lattner
e589d360a1 Stabilize 'getDwarfRegNumFull' output to not depend on random memory 
orders, part of PR2590

llvm-svn: 55359
 2008-08-26 06:43:25 +00:00
Owen Anderson
9c207563a1 Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes. 
llvm-svn: 55349
 2008-08-26 01:22:59 +00:00
Owen Anderson
7e677167d6 Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch. 
llvm-svn: 55347
 2008-08-26 00:42:26 +00:00
Owen Anderson
9264f41ef2 Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return 
type down.  This is not currently used.

llvm-svn: 55345
 2008-08-25 23:58:18 +00:00
Owen Anderson
19b73e58e8 Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns 
with return types that differ from their input types.  This is not yet used.

llvm-svn: 55344
 2008-08-25 23:43:09 +00:00
Owen Anderson
27491bbf2c Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.

llvm-svn: 55325
 2008-08-25 20:20:32 +00:00
Dan Gohman
a9d5f9b006 Move the point at which FastISel taps into the SelectionDAGISel 
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
 2008-08-23 02:25:05 +00:00
Dan Gohman
46c93eebcd Add a few comments. 
llvm-svn: 55157
 2008-08-22 00:28:15 +00:00
Dan Gohman
a398d11527 Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156
 2008-08-22 00:20:26 +00:00
Dan Gohman
a6e647dd7c Basic fast-isel support for instructions with constant int operands. 
llvm-svn: 55099
 2008-08-21 01:41:07 +00:00
Dan Gohman
e628777073 Remove the code that limited FastISel to certain fixed signatures. 
llvm-svn: 55096
 2008-08-21 00:35:26 +00:00