20615 Commits

Author SHA1 Message Date
Eric Christopher
7dd3f8b252 Add support for DW_FORM_dataN and DW_FORM_udata to the DIE hashing
algorithm. Update the split dwarf hashing testcase accordingly - this
should be the last time that the hash of an empty file changes.

llvm-svn: 189427
2013-08-28 00:10:38 +00:00
Eric Christopher
2cbbfd0acc Use DW_FORM_sdata for signed constant values and udata on occasion
when we can. Migrate from using blocks when we're adding just a
single attribute and floating point values are an unsigned, not signed,
bag of bits.

Update all test cases accordingly.

llvm-svn: 189419
2013-08-27 23:49:04 +00:00
Eric Christopher
25f1de3317 Move some debug testcases to the debug info directory.
llvm-svn: 189418
2013-08-27 23:48:57 +00:00
Peter Collingbourne
e16a469093 DataFlowSanitizer: Implement trampolines for function pointers passed to custom functions.
Differential Revision: http://llvm-reviews.chandlerc.com/D1503

llvm-svn: 189408
2013-08-27 22:09:06 +00:00
David Majnemer
8b1b2dd0cd [ms-inline asm] Support offsets after segment registers
Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'

Reviewers: craig.topper, rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1470

llvm-svn: 189407
2013-08-27 21:56:17 +00:00
Joerg Sonnenberger
b2cc802497 Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.

llvm-svn: 189400
2013-08-27 20:23:19 +00:00
Joey Gouly
c935e7defb [ARMv8] Add MC support for the new load/store acquire/release instructions.
llvm-svn: 189388
2013-08-27 17:38:16 +00:00
Elena Demikhovsky
471e732613 AVX-512: added conversion instructions.
llvm-svn: 189349
2013-08-27 13:54:04 +00:00
Tim Northover
5802bd3e8d DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap
We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N),
const), but this is only valid if the bits above 16 on the source pattern are
0, the checks we were doing on this were slightly wrong before.

llvm-svn: 189348
2013-08-27 13:46:45 +00:00
Joey Gouly
740189864d [ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.

llvm-svn: 189341
2013-08-27 11:24:16 +00:00
Tim Northover
24c6842d69 ARM: add natural patterns for vaddhl and vsubhl.
These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.

llvm-svn: 189335
2013-08-27 10:31:36 +00:00
Michel Danzer
084b7ef3da R600/SI: Enable local-memory-two-objects lit test
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 189334
2013-08-27 10:28:26 +00:00
Daniel Sanders
87ee4173d5 [mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v when non-byte vectors are used.
Note that all of these tests use ld.b and st.b for the loads and stores
regardless of the data size. This is because the definition of bitcast is
equivalent to a store/load sequence and DAG combiner accordingly folds bitcasts
to/from v16i8 into the load/store nodes to product load/store nodes with
type v16i8.

llvm-svn: 189333
2013-08-27 10:16:17 +00:00
Daniel Sanders
00e8a9cb19 [mips][msa] Added spill/reload support
llvm-svn: 189332
2013-08-27 10:04:21 +00:00
Richard Sandiford
b585b1e48e [SystemZ] Extend memcpy and memset support to all constant lengths
Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs.
Lengths above that threshold use a loop to handle X*256 bytes followed
by a single MVC to handle the excess (if any).  This loop will also be
needed in future when support for variable lengths is added.

Because the same tablegen classes are used to define MVC and CLC,
the patch also has the side-effect of defining a pseudo loop instruction
for CLC.  That instruction isn't used yet (and wouldn't be handled correctly
if it were).  I'm planning to use it soon though.

llvm-svn: 189331
2013-08-27 09:54:29 +00:00
Daniel Sanders
b2c1c16a0a [mips][msa] Added bitconverts for vector types for big and little-endian
llvm-svn: 189330
2013-08-27 09:40:30 +00:00
Elena Demikhovsky
8e8304bffc AVX-512: Added FMA instructions.
llvm-svn: 189326
2013-08-27 08:39:25 +00:00
Kai Nacke
aa4accce49 Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s

Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.

llvm-svn: 189309
2013-08-27 04:16:16 +00:00
Eric Christopher
a58048789c Add derived from source.
llvm-svn: 189301
2013-08-27 00:46:28 +00:00
Eric Christopher
f937a0a2e2 Add a testcase to ensure that the pubnames section uses an offset
off of the debug_info section even when split dwarf is enabled.

llvm-svn: 189300
2013-08-27 00:36:19 +00:00
Matt Arsenault
0c955e9568 Fix lint assert on integer vector division
llvm-svn: 189290
2013-08-26 23:29:33 +00:00
Eric Christopher
04da79d6a3 Treat the pubtypes section similarly to the pubnames section and emit
it by default under linux or when we're trying to keep compatibility
with old gdb versions.

Fix testcase for option name change.

llvm-svn: 189289
2013-08-26 23:24:35 +00:00
Matt Arsenault
c32a5a3d46 Fix inserting instructions before last in bundle.
The builder inserts from before the insert point,
not after, so this would insert before the last
instruction in the bundle instead of after it.

I'm not sure if this can actually be a problem
with any of the current insertions.

llvm-svn: 189285
2013-08-26 23:08:37 +00:00
Manman Ren
20ae2817fa Debug Info: add an identifier field to DICompositeType.
DICompositeType will have an identifier field at position 14. For now, the
field is set to null in DIBuilder.
For DICompositeTypes where the template argument field (the 13th field)
was optional, modify DIBuilder to make sure the template argument field is set.
Now DICompositeType has 15 fields.

Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode.
Update verifier to check that DICompositeType has 15 fields and the last
field is null or a MDString.

Update testing cases to include an extra field for DICompositeType.
The identifier field will be used by type uniquing so a front end can
genearte a DICompositeType with a unique identifer.

llvm-svn: 189282
2013-08-26 22:39:55 +00:00
Nadav Rotem
7d4e24e1f4 LoopVectorize: Implement partial loop unrolling when vectorization is not profitable.
This patch enables unrolling of loops when vectorization is legal but not profitable.
We add a new class InnerLoopUnroller, that extends InnerLoopVectorizer and replaces some of the vector-specific logic with scalars.

This patch does not introduce any runtime regressions and improves the following workloads:

SingleSource/Benchmarks/Shootout/matrix -22.64%
SingleSource/Benchmarks/Shootout-C++/matrix -13.06%
External/SPEC/CINT2006/464_h264ref/464_h264ref  -3.99%
SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding -1.95%

llvm-svn: 189281
2013-08-26 22:33:26 +00:00
Jim Grosbach
b5dae7e207 ARM: Enable machine verifier for a few more tests.
Now that fast-isel is in better shape, we can enable the machine
verifier for these tests, too.

rdar://12594152

llvm-svn: 189275
2013-08-26 20:22:08 +00:00
Jim Grosbach
f88c4f8dbc ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

llvm-svn: 189274
2013-08-26 20:22:05 +00:00
Jim Grosbach
0cc0fac41e ARM: FastISel verifier error cleanup.
Constant pool and global value reference instructions need more
restricted register classes than plain GPR.

rdar://12594152

llvm-svn: 189270
2013-08-26 20:07:29 +00:00
Bill Schmidt
84204dd94d [PowerPC] More fast-isel chunks (returns and integer extends)
Incremental improvement to fast-isel for PPC64.  This allows us to
select on ret, sext, and zext.  Filling in sext/zext improves some of
the existing logic in handling compare-immediates that needed extends.

A simplified return convention for fast-isel is also added to the
PPC64 calling conventions.  All call/return processing for DAG
selection is handled with custom code, so there isn't an existing CC
to rely on here.  The include of PPCGenCallingConv.inc causes compiler
warnings due to the 32-bit calling conventions that are not used, so
the dummy function "usePPC32CCs()" is added here to silence those.

Test cases for the return and extend logic are added.

llvm-svn: 189266
2013-08-26 19:42:51 +00:00
Matt Arsenault
adea897e71 Forgot to add slp threshold to test
llvm-svn: 189248
2013-08-26 18:08:35 +00:00
Matt Arsenault
fe57252c78 Vectorize starting from insertelements building a vector
llvm-svn: 189233
2013-08-26 17:56:35 +00:00
Tom Stellard
f7fd8102dd SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()
If we have a binary operation like ISD:ADD, we can set the result type
equal to the result type of one of its operands rather than using
TargetLowering::getPointerTy().

Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary
operation can be replaced with:
DAG.getConstant(C, OtherOperand.getValueType());

llvm-svn: 189227
2013-08-26 15:06:10 +00:00
Tom Stellard
471cae1398 R600: Add support for vector local memory loads
llvm-svn: 189226
2013-08-26 15:06:04 +00:00
Tom Stellard
951bdd0d80 R600: Add support for i8 and i16 local memory loads
llvm-svn: 189225
2013-08-26 15:05:59 +00:00
Tom Stellard
dec9289d7b SelectionDAG: Use correct pointer size when splitting vector stores
llvm-svn: 189224
2013-08-26 15:05:55 +00:00
Tom Stellard
38c07cc5d7 R600: Add support for i8 and i16 local memory stores
llvm-svn: 189223
2013-08-26 15:05:49 +00:00
Tom Stellard
743d74f1b3 R600: Add support for v4i32 and v2i32 local stores
llvm-svn: 189222
2013-08-26 15:05:44 +00:00
Tom Stellard
1287fd01c3 SelectionDAG: Use correct pointer size when lowering function arguments v2
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

llvm-svn: 189221
2013-08-26 15:05:36 +00:00
Elena Demikhovsky
4333460954 AVX-512: Added shuffle instructions -
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.

llvm-svn: 189215
2013-08-26 12:45:35 +00:00
Vladimir Medic
78876a9ef9 This patch implements trap instructions for mips. The test cases are added.
llvm-svn: 189213
2013-08-26 10:02:40 +00:00
Bill Schmidt
c010bfbf75 [PowerPC] Add fast-isel branch and compare selection.
First chunk of actual fast-isel selection code.  This handles direct
and indirect branches, as well as feeding compares for direct
branches.  PPCFastISel::PPCEmitIntExt() is just roughed in and will be
expanded in a future patch.  This also corrects a problem with
selection for constant pool entries in JIT mode or with small code
model.

llvm-svn: 189202
2013-08-25 22:33:42 +00:00
Craig Topper
3f15756092 First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.

Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.

llvm-svn: 189201
2013-08-25 22:23:38 +00:00
Venkatraman Govindaraju
a3fc2b00cc [Sparc] Add long double (f128) instructions to sparc backend.
llvm-svn: 189198
2013-08-25 18:30:06 +00:00
Venkatraman Govindaraju
1d08468931 [Sparc] Added V9's extra floating point registers and their aliases.
llvm-svn: 189195
2013-08-25 17:03:02 +00:00
Elena Demikhovsky
15c3ef8486 AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors
llvm-svn: 189189
2013-08-25 12:54:30 +00:00
Reed Kotler
8738736cec Start to add the LLVM builtins to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted

Resubmit this patch. The target triple needs to be added to the test so that 
clang does not tell the backend the wrong target when the host is BSD. There
is a clang bug in here somewhere that I need to track down. At Mips this
has been filed internally as a bug.

llvm-svn: 189186
2013-08-25 02:40:25 +00:00
Shuxin Yang
e1653d8592 Revert 189161
llvm-svn: 189176
2013-08-24 17:53:16 +00:00
Reed Kotler
42e1d3fb15 Start to add the builtind to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted.

llvm-svn: 189161
2013-08-24 01:24:44 +00:00
Justin Holewinski
f9ed859e28 [NVPTX] Re-enable assembly printing support for inline assembly
This support was removed by accident during the MC conversion

llvm-svn: 189160
2013-08-24 01:17:23 +00:00
Rafael Espindola
8648d2d87d Update test to use rdrnd instead of rdrand.
llvm-svn: 189146
2013-08-23 20:49:02 +00:00