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Author SHA1 Message Date
Bill Wendling
834bb83a41 Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.

llvm-svn: 141031
 2011-10-03 21:25:38 +00:00
Akira Hatanaka
0a697c10ae Move CHECK after entry label. 
llvm-svn: 141030
 2011-10-03 21:24:30 +00:00
Akira Hatanaka
76c268271d Add support for 64-bit logical NOR. 
llvm-svn: 141029
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
ae50204423 Add support for 64-bit count leading ones and zeros instructions. 
llvm-svn: 141028
 2011-10-03 21:16:50 +00:00
Bill Wendling
1ad4ffcaa2 Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair. 
llvm-svn: 141026
 2011-10-03 21:15:28 +00:00
Jim Grosbach
21a9f8f50f ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Akira Hatanaka
6c6ff6fde7 Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Devang Patel
659746207c Add C api for Instruction->eraseFromParent(). 
llvm-svn: 141023
 2011-10-03 20:59:18 +00:00
Jim Grosbach
0e385170ee Update test for 141010. 
llvm-svn: 141022
 2011-10-03 20:58:08 +00:00
Jim Grosbach
c7a9669343 Thumb2 ADD/SUB can take SP as a destination register. 
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

llvm-svn: 141020
 2011-10-03 20:51:59 +00:00
Akira Hatanaka
7e1775fdd6 Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer 
registers.

llvm-svn: 141019
 2011-10-03 20:38:08 +00:00
Akira Hatanaka
e3c1d7eac0 Add support for 64-bit integer multiply instructions. 
llvm-svn: 141017
 2011-10-03 20:01:11 +00:00
Akira Hatanaka
3f3d72c052 Add definitions of instructions which move values between 64-bit integer 
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015
 2011-10-03 19:28:44 +00:00
Bob Wilson
3cbd97d1a6 Find the strip tool that works with the specified SDKROOT. rdar://10165908 
llvm-svn: 141013
 2011-10-03 18:48:16 +00:00
Jim Grosbach
1651804363 Tidy up a bit. Formatting. 
llvm-svn: 141010
 2011-10-03 17:59:31 +00:00
Craig Topper
df04bee9b2 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
llvm-svn: 141007
 2011-10-03 17:28:23 +00:00
Eric Christopher
75a56b2f1f Whitespace. 
llvm-svn: 141005
 2011-10-03 15:49:20 +00:00
Eric Christopher
d34e1d8bb6 Typo. 
llvm-svn: 141004
 2011-10-03 15:49:16 +00:00
Rafael Espindola
4700f53cee Add the returns_twice attribute to LLVM. 
llvm-svn: 141001
 2011-10-03 14:45:37 +00:00
Craig Topper
4456c94f70 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
llvm-svn: 140997
 2011-10-03 08:14:29 +00:00
Craig Topper
a3372bd949 Test updates that were supposed to go with r140993. 
llvm-svn: 140994
 2011-10-03 07:53:59 +00:00
Craig Topper
7a5eafab6c Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode. 
llvm-svn: 140993
 2011-10-03 07:51:09 +00:00
Nick Lewycky
4898eef762 Reapply r140979 with fix! We never did get a testcase, but careful review of the 
logic by David Meyer revealed this bug.

llvm-svn: 140992
 2011-10-03 07:10:45 +00:00
Torok Edwin
b7495041db attempt to fix ocaml bindings: landing pads 
llvm-svn: 140991
 2011-10-03 06:41:46 +00:00
Nick Lewycky
79fec8116f Revert r140979 due to reports of bootstrap failure. 
llvm-svn: 140980
 2011-10-03 05:14:59 +00:00
Nick Lewycky
a760a29395 Add one more case we compute a max trip count. 
llvm-svn: 140979
 2011-10-03 01:03:57 +00:00
Craig Topper
f776e3b410 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
llvm-svn: 140974
 2011-10-02 21:08:12 +00:00
Craig Topper
5c8feca34f Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
llvm-svn: 140971
 2011-10-02 16:56:09 +00:00
Nick Lewycky
7cd1bfb89d Add a new icmp+select optz'n. Also shows off the load(cst) folding added in 
r140966.

llvm-svn: 140969
 2011-10-02 10:37:37 +00:00
Nick Lewycky
3282ef025d Enhance a couple places where we were doing constant folding of instructions, 
but not load instructions. Noticed by inspection.

llvm-svn: 140966
 2011-10-02 09:12:55 +00:00
Craig Topper
7b5028ec10 Fix typo in r140954. 
llvm-svn: 140962
 2011-10-02 04:54:26 +00:00
Ted Kremenek
744f9cc17c Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit. 
llvm-svn: 140959
 2011-10-02 01:47:07 +00:00
Craig Topper
43fd621df8 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
Chad Rosier
2cb0d1eddf Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." 
to appease nightly testers.  Not quite there yet.

llvm-svn: 140953
 2011-10-01 19:30:36 +00:00
Nadav Rotem
40ed18ae3e Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit. 
llvm-svn: 140952
 2011-10-01 18:39:28 +00:00
Peter Collingbourne
01246536d9 Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
 2011-10-01 16:41:13 +00:00
Bill Wendling
d6d232142d No one should be using the method directly. Assert if they do. 
llvm-svn: 140947
 2011-10-01 12:47:34 +00:00
Bill Wendling
3ce912d5b8 Add a convenience method to tell if two things are equal. 
llvm-svn: 140946
 2011-10-01 12:44:28 +00:00
Bill Wendling
a23068ec02 Use the ARMConstantPoolMBB class to handle the MBB values. 
llvm-svn: 140943
 2011-10-01 09:30:42 +00:00
Bill Wendling
a925d1339f Add ARMConstantPoolMBB to hold an MBB value in the constant pool. 
llvm-svn: 140942
 2011-10-01 09:19:10 +00:00
Bill Wendling
aab50632f6 Remove dead code. 
llvm-svn: 140941
 2011-10-01 09:05:12 +00:00
Bill Wendling
0049e4398d Remove now dead methods and ivar. 
llvm-svn: 140940
 2011-10-01 09:04:18 +00:00
Bill Wendling
c7bf6da86d Use the new ARMConstantPoolSymbol class to handle external symbols. 
llvm-svn: 140939
 2011-10-01 08:58:29 +00:00
Bill Wendling
4563d806a7 Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. 
llvm-svn: 140938
 2011-10-01 08:36:59 +00:00
Bill Wendling
67b6d8a185 Remove now dead methods and ivar from ARMConstantPoolValue. 
llvm-svn: 140937
 2011-10-01 08:02:05 +00:00
Bill Wendling
1d585d7961 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Bill Wendling
9356ee3bd7 Some more refactoring. 
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.

llvm-svn: 140935
 2011-10-01 07:52:37 +00:00
Bill Wendling
9ad0742c3f Add a Create method that accepts 'kind' and 'pcadj' arguments. 
llvm-svn: 140934
 2011-10-01 06:44:24 +00:00
Bill Wendling
33b0c55f4d Refactoring: Separate out the ARM constant pool Constant from the ARM constant 
pool value.

It's not used right now, but will be soon.

llvm-svn: 140933
 2011-10-01 06:40:33 +00:00