instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.
llvm-svn: 93210
- getToken is modeled after StringRef::split but it can split on multiple
separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
same behaviour as getToken.
llvm-svn: 93161
Compare the dominance information calculated using a dominance tree walk to the
information calculated based on DFS numbers, if XDEBUG is enabled.
llvm-svn: 92969
Remove a FIXME and unify code that was necessary to work around broken
updateDFSNumbers(). Before updateDFSNumbers() did not work correctly for post
dominators.
llvm-svn: 92968
The DFS number calculation for postdominators was broken. In the case of
multiple exits that form the post dominator root nodes, do not iterate over
all exits, but start from the virtual root node. Otherwise bbs, that are not
post dominated by any exit but by the virtual root node, will never be assigned
a DFS number.
llvm-svn: 92967
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
llvm-svn: 92849
memcpy, memset and other intrinsics that only access their arguments
to be readnone if the intrinsic's arguments all point to local memory.
This improves the testcase in the README to readonly, but it could in
theory be made readnone, however this would involve more sophisticated
analysis that looks through the memcpy.
llvm-svn: 92829
An instruction like this:
%reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0
Must be replaced with this when substituting physical registers:
%S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>
llvm-svn: 92812
a single pointer (PointerIntPair) member. In "small" mode, the
pointer field is reinterpreted as a set of bits. In "large" mode,
the pointer points to a heap-allocated object.
Also, give BitVector empty and swap functions.
And, add some simple unittests for BitVector and SmallBitVector.
llvm-svn: 92730
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
