Commit Graph

82678 Commits

Author SHA1 Message Date
Chris Lattner
8b71fa09ec enhance the logic for looking through tailcalls to look through transparent casts
in multiple-return value scenarios, like what happens on X86-64 when returning
small structs.

llvm-svn: 157800
2012-06-01 05:29:15 +00:00
Craig Topper
6343cc814e Tidy up. Remove trailing spaces and fix the worst of the 80 column violations.
llvm-svn: 157799
2012-06-01 05:24:29 +00:00
Chris Lattner
9f7a47d886 enhance getNoopInput to know about vector<->vector bitcasts of legal
types, as well as int<->ptr casts.  This allows us to tailcall functions
with some trivial casts between the call and return (i.e. because the
return types disagree).

llvm-svn: 157798
2012-06-01 05:16:33 +00:00
Chris Lattner
748ecee801 add some simple 64-bit tail call tests.
llvm-svn: 157797
2012-06-01 05:03:31 +00:00
Chris Lattner
99d5a0bfde rearrange some logic, no functionality change.
llvm-svn: 157796
2012-06-01 05:01:15 +00:00
Chris Lattner
f4a7be0c55 merge some tests.
llvm-svn: 157795
2012-06-01 05:00:54 +00:00
Chris Lattner
39d2bf08f8 rename test
llvm-svn: 157794
2012-06-01 04:58:50 +00:00
Manman Ren
f30d4765c5 ARM: support struct byval in llvm
We handle struct byval by inserting a pseudo op, which will be expanded to a
loop at ExpandISelPseudos.
A separate patch for clang will be submitted to enable struct byval.

rdar://9877866

llvm-svn: 157793
2012-06-01 02:44:42 +00:00
Michael J. Spencer
156a5bf10e Fix 80 columns.
llvm-svn: 157788
2012-06-01 00:58:41 +00:00
Eric Christopher
2cff8a57a0 Add support for enum forward declarations.
Part of rdar://11570854

llvm-svn: 157786
2012-06-01 00:22:32 +00:00
Chad Rosier
901c912b26 Put the shiny new MCSubRegIterator to work.
llvm-svn: 157783
2012-06-01 00:02:08 +00:00
Nuno Lopes
3a79c6f953 add -bounds-checking-multiple-traps option to make one trap BB per check
disabled by default for now; we can discusse the default value (& name) later

llvm-svn: 157777
2012-05-31 22:58:48 +00:00
Nuno Lopes
baa73f38ba revamp BoundsChecking considerably:
- compute size & offset at the same time. The side-effects of this are that we now support negative GEPs. It's now approaching a phase that it can be reused by other passes (e.g., lowering of the objectsize intrinsic)
 - use APInt throughout to handle wrap-arounds
 - add support for PHI instrumentation
 - add a cache (required for recursive PHIs anyway)
 - remove hoisting support for now, since it was wrong in a few cases

sorry for the churn here.. tests will follow soon.

llvm-svn: 157775
2012-05-31 22:45:40 +00:00
Benjamin Kramer
2f57459340 IntrusiveRefCntPtr: Simplify operator= as suggested by Richard Smith.
This way the constructors do all the hard work. No intended functionality change.

llvm-svn: 157773
2012-05-31 22:25:25 +00:00
Owen Anderson
060176473a Make this testcase independent of register allocation.
llvm-svn: 157761
2012-05-31 18:07:02 +00:00
Jakob Stoklund Olesen
a77ddf1405 Add support for return value promotion in X86 calling conventions.
Patch by Yiannis Tsiouris!

llvm-svn: 157757
2012-05-31 17:28:20 +00:00
Jakob Stoklund Olesen
19569cbcde Didn't mean to export this function.
llvm-svn: 157756
2012-05-31 17:21:27 +00:00
Manman Ren
82e2c9debf X86: replace SUB with CMP if possible
This patch will optimize the following
        movq    %rdi, %rax
        subq    %rsi, %rax
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax
to
        cmpq    %rsi, %rdi
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023
llvm-svn: 157755
2012-05-31 17:20:29 +00:00
Jakob Stoklund Olesen
dc9a46b651 Add a PrintRegUnit helper similar to PrintReg.
Reg-units are named after their root registers, and most units have a
single root, so they simply print as 'AL', 'XMM0', etc. The rare dual
root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ...

The printing piggybacks on the existing register name tables, so no
extra const data space is required.

llvm-svn: 157754
2012-05-31 17:18:29 +00:00
Jakob Stoklund Olesen
e79316648d Emit register unit root tables.
Each register unit has one or two root registers. The full set of
registers containing a given register unit can be computed as the union
of the root registers and their super-registers.

Provide an MCRegUnitRootIterator class to enumerate the roots.

llvm-svn: 157753
2012-05-31 17:18:26 +00:00
Joel Jones
f5c5c3cd31 Fix typos
llvm-svn: 157752
2012-05-31 17:11:25 +00:00
Rafael Espindola
efd9f38c2d Fix typos noticed by Benjamin Kramer.
Also make the checks stronger and test that we reject ranges that overlap
a previous wrapped range.

llvm-svn: 157749
2012-05-31 16:04:26 +00:00
Benjamin Kramer
cb686400fb X86: Rename the CLMUL target feature to PCLMUL.
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

llvm-svn: 157745
2012-05-31 14:34:17 +00:00
Rafael Espindola
26ddf2b0be Require intervals in the range metadata to be in a canonical form: They must
be non contiguous, non overlapping and sorted by the lower end.

While this is technically a backward incompatibility, every frontent currently
produces range metadata with a single interval and we don't have any pass
that merges intervals yet, so no existing bitcode files should be rejected by
this.

llvm-svn: 157741
2012-05-31 13:45:46 +00:00
Elena Demikhovsky
194da7364d Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.

llvm-svn: 157737
2012-05-31 09:20:20 +00:00
Duncan Sands
8099422e17 Enhance the sinking code to handle diamond patterns. Patch by
Carlo Alberto Ferraris.

llvm-svn: 157736
2012-05-31 08:09:49 +00:00
Craig Topper
c6bd90e646 Add intrinsic for pclmulqdq instruction.
llvm-svn: 157731
2012-05-31 04:37:40 +00:00
Akira Hatanaka
9d64361208 Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
2012-05-31 02:59:44 +00:00
Eric Christopher
a50a5fb980 Fix typo in assembly directive. Noticed by inspection.
llvm-svn: 157726
2012-05-31 00:53:18 +00:00
Akira Hatanaka
0f0b2fa29f Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
llvm-svn: 157725
2012-05-31 00:49:56 +00:00
Jakob Stoklund Olesen
f39378b6d8 Avoid depending on list orders and register numbering.
This code is covered by test/CodeGen/ARM/arm-modifier.ll.

llvm-svn: 157720
2012-05-30 23:00:43 +00:00
Jakob Stoklund Olesen
b27db3628f Extract some pointer hacking to a function.
Switch to MCSuperRegIterator while we're there.

llvm-svn: 157717
2012-05-30 22:40:03 +00:00
Jakob Stoklund Olesen
8a558631c0 Prioritize smaller register classes for urgent evictions.
It helps compile exotic inline asm. In the test case, normal GR32
virtual registers use up eax-edx so the final GR32_ABCD live range has
no registers left. Since all the live ranges were tiny, we had no way of
prioritizing the smaller register class.

This patch allows tiny unspillable live ranges to be evicted by tiny
unspillable live ranges from a smaller register class.

<rdar://problem/11542429>

llvm-svn: 157715
2012-05-30 21:46:58 +00:00
Jakob Stoklund Olesen
cf597f5c30 Print uint16_t numbers without a sign.
It seems I broke C++11.

llvm-svn: 157711
2012-05-30 19:20:19 +00:00
Eric Christopher
c2eb5a6ee6 Add support for the mips inline asm 'm' output modifier.
Patch by Jack Carter.

llvm-svn: 157709
2012-05-30 19:05:19 +00:00
Owen Anderson
38e510d831 Switch the canonical FMA term operand order to match both the comment I wrote and the usual LLVM convention.
llvm-svn: 157708
2012-05-30 18:54:50 +00:00
Owen Anderson
49ddb93c30 Teach DAGCombine to canonicalize the position of a constant in the term operands of an FMA node.
llvm-svn: 157707
2012-05-30 18:50:39 +00:00
Chad Rosier
26331ee2c8 Remove extra space.
llvm-svn: 157706
2012-05-30 18:47:55 +00:00
David Blaikie
57af7f0167 Reinstate -O3 for LTO.
This broke in r144788 when the CodeGenOpt option was moved from everywhere else
(specifically, from addPassesToEmitFile) to createTargetMachine. Since
LTOCodeGenerator wasn't passing the 4th argument, when the 4th parameter became
the 3rd, it silently continued to compile (int->bool conversion) but meant
something completely different.

This change preserves the existing (accidental) and previous (default)
semantics of the addPassesToEmitFile and restores the previous/intended
CodeGenOpt argument by passing it appropriately to createTargetMachine.

(discovered by pending changes to -Wconversion to catch constant->bool
conversions)

llvm-svn: 157705
2012-05-30 18:42:51 +00:00
Benjamin Kramer
3fecff028d Make sure that we're dealing with a binary SCEVExpr when simplifying.
llvm-svn: 157704
2012-05-30 18:42:43 +00:00
Jakob Stoklund Olesen
2dca201f54 Fix some uses of getSubRegisters() to use getSubReg() instead.
It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703
2012-05-30 18:40:49 +00:00
Jakob Stoklund Olesen
0bc2a65aad Remove some redundant tests.
An empty list is not represented as a null pointer. Let TRI do its own
shortcuts.

llvm-svn: 157702
2012-05-30 18:38:56 +00:00
Benjamin Kramer
3578c169bf Teach SCEV's icmp simplification logic that a-b == 0 is equivalent to a == b.
This also required making recursive simplifications until
nothing changes or a hard limit (currently 3) is hit.

With the simplification in place indvars can canonicalize
loops of the form
for (unsigned i = 0; i < a-b; ++i)
into
for (unsigned i = 0; i != a-b; ++i)
which used to fail because SCEV created a weird umax expr
for the backedge taken count.

llvm-svn: 157701
2012-05-30 18:32:23 +00:00
Chris Lattner
1d39403e7b it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly. Just optimize 3 more.
llvm-svn: 157699
2012-05-30 18:08:02 +00:00
Chris Lattner
505bcf70a0 Extend the (abi-irrelevant) return convention to be able to return more than two values in
integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.

llvm-svn: 157698
2012-05-30 17:50:14 +00:00
Chad Rosier
80159b26a5 [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157696
2012-05-30 17:23:22 +00:00
Jakob Stoklund Olesen
67b7a47013 Add MCRegisterInfo::RegListIterator.
Also add subclasses MCSubRegIterator, MCSuperRegIterator, and
MCRegAliasIterator.

These iterators provide an abstract interface to the MCRegisterInfo
register lists so the internal representation can be changed without
changing all clients.

llvm-svn: 157695
2012-05-30 16:36:28 +00:00
Benjamin Kramer
df046ac8f9 Mark insertq/extrq intrinsic readnone.
llvm-svn: 157688
2012-05-30 13:44:25 +00:00
Benjamin Kramer
11fa8a91e7 Port support for SSE4a extrq/insertq to the old jit code emitter.
llvm-svn: 157685
2012-05-30 09:13:55 +00:00
Benjamin Kramer
43f299647a Remove little semicolon that caused a lot of warnings.
llvm-svn: 157684
2012-05-30 09:13:49 +00:00