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4590 Commits

Author SHA1 Message Date
Cameron Zwarich
af47f4a117 A CCState was being created without setting whether it is in the Call or Prologue state, 
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811
 2011-06-09 22:30:07 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Andrew Trick
a46c28e96c Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR. 
rdar://problem/9556069

llvm-svn: 132699
 2011-06-07 00:08:49 +00:00
Eric Christopher
e831655dd9 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
 2011-06-03 17:24:37 +00:00
Eli Friedman
eae10d6163 Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157

llvm-svn: 132522
 2011-06-03 01:13:19 +00:00
Eric Christopher
d68494ffdd Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939

llvm-svn: 132510
 2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
409986a648 Flag unallocatable register classes instead of giving them empty 
allocation orders.

llvm-svn: 132509
 2011-06-02 23:07:24 +00:00
Tanya Lattner
aa1f6df650 Fix encoding for VEXTdf. 
llvm-svn: 132486
 2011-06-02 21:25:24 +00:00
Jakob Stoklund Olesen
25716baae0 Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

llvm-svn: 132455
 2011-06-02 05:43:46 +00:00
Rafael Espindola
ee123951a2 Don't hardcode the %reg format in the streamer. 
llvm-svn: 132451
 2011-06-02 02:34:55 +00:00
Bruno Cardoso Lopes
0bdb365634 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value 
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324
 2011-05-31 03:33:27 +00:00
Rafael Espindola
33f7d7f9fa Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

llvm-svn: 132317
 2011-05-30 20:20:15 +00:00
John McCall
64ff21faa7 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.

llvm-svn: 132295
 2011-05-29 19:50:32 +00:00
John McCall
ffdb2d5e70 I didn't mean to commit these residues of a personal project. 
llvm-svn: 132293
 2011-05-29 19:41:56 +00:00
John McCall
46c7b963b2 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

llvm-svn: 132291
 2011-05-29 19:39:04 +00:00
Cameron Zwarich
72e034c331 Fix ARM fast isel to correctly flag memory operands to stores. This fixes 
-verify-machineinstrs failures on several tests.

llvm-svn: 132268
 2011-05-28 20:34:49 +00:00
Bruno Cardoso Lopes
6d5e369a10 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

llvm-svn: 132248
 2011-05-28 04:07:29 +00:00
Eric Christopher
a2fa6edef9 This actually starts at offset 0, not 1. 
llvm-svn: 132246
 2011-05-28 03:16:22 +00:00
Eric Christopher
000dd7d0e6 Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242
 2011-05-28 01:40:44 +00:00
Cameron Zwarich
cd3c1b5829 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

llvm-svn: 132235
 2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
93eae0fd19 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb 
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

llvm-svn: 132233
 2011-05-27 23:46:09 +00:00
Rafael Espindola
2230168a0f Make size computation less brittle. 
llvm-svn: 132222
 2011-05-27 22:05:41 +00:00
Evan Cheng
0fcb465bab Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
llvm-svn: 132211
 2011-05-27 20:11:27 +00:00
Eli Friedman
560532051b Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 
llvm-svn: 132194
 2011-05-27 18:02:04 +00:00
Eric Christopher
0e12efbed1 Make the branch encoding for tBcc more obvious that it's a 4-byte opcode 
followed by a conditional and imm8.

llvm-svn: 132179
 2011-05-27 03:50:53 +00:00
Eric Christopher
cfce589451 Fix comment. 
llvm-svn: 132178
 2011-05-27 03:46:51 +00:00
Eric Christopher
4fc5b88850 Reorganize these slightly according to operand type. 
llvm-svn: 132128
 2011-05-26 18:22:26 +00:00
Cameron Zwarich
9c871755b6 Mark tBX as an indirect branch rather than a return. 
llvm-svn: 132107
 2011-05-26 03:41:12 +00:00
Eli Friedman
93ffb875ad Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099
 2011-05-25 23:49:02 +00:00
Cameron Zwarich
9c19995747 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
llvm-svn: 132086
 2011-05-25 21:53:50 +00:00
Eric Christopher
e02bd15dbc Clean up comment a bit. 
llvm-svn: 132083
 2011-05-25 21:19:19 +00:00
Eric Christopher
807da21e47 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939

llvm-svn: 132081
 2011-05-25 20:51:58 +00:00
Eli Friedman
2bdd096540 Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values. 
llvm-svn: 132073
 2011-05-25 19:09:45 +00:00
Cameron Zwarich
5c410bd5f6 Restore an accidentally removed comment. 
llvm-svn: 132044
 2011-05-25 04:48:17 +00:00
Cameron Zwarich
4f47b296d8 Move some code to a more logical place. 
llvm-svn: 132043
 2011-05-25 04:45:29 +00:00
Cameron Zwarich
beae5f20e8 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

llvm-svn: 132042
 2011-05-25 04:45:27 +00:00
Cameron Zwarich
5a32e53e3f Change the order of tBX's operands so that the predicate operands come after the 
target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

llvm-svn: 132041
 2011-05-25 04:45:23 +00:00
Cameron Zwarich
08753a605b Rename tBX_Rm to tBX. 
llvm-svn: 132040
 2011-05-25 04:45:20 +00:00
Cameron Zwarich
d9707488bb Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
 2011-05-25 04:45:14 +00:00
Bruno Cardoso Lopes
3a4aae57f4 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026
 2011-05-25 00:35:03 +00:00
Eric Christopher
4f193f9555 Implement the arm 'L' asm modifier. 
Part of rdar://9119939

llvm-svn: 132024
 2011-05-24 23:27:13 +00:00
Eric Christopher
a6d7ccb170 Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939

llvm-svn: 132023
 2011-05-24 23:15:43 +00:00
Eric Christopher
4783e5e316 Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.

llvm-svn: 132015
 2011-05-24 22:27:43 +00:00
Eric Christopher
03965fa3b6 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657

llvm-svn: 132011
 2011-05-24 22:10:34 +00:00
Cameron Zwarich
5a416bda73 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

llvm-svn: 131894
 2011-05-23 01:57:17 +00:00
Renato Golin
759db3cbe3 RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. 
llvm-svn: 131868
 2011-05-22 21:41:23 +00:00
Johnny Chen
6e8aeaa2f4 Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx 
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.

llvm-svn: 131859
 2011-05-22 17:51:04 +00:00
Rafael Espindola
f114810ec8 adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751
 2011-05-20 20:10:34 +00:00
Rafael Espindola
27dbdbdf4c fixes target address tBL and tBLX and sets relocation type 
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

llvm-svn: 131748
 2011-05-20 20:01:01 +00:00
Evan Cheng
9dbb570612 Revert accidental commit. 
llvm-svn: 131739
 2011-05-20 17:38:48 +00:00