Commit Graph

2647 Commits

Author SHA1 Message Date
Dan Gohman
dae85a0de0 When handling raw_ostream errors manually, use clear_error() so that
raw_ostream doesn't try to do its own error handling.

llvm-svn: 104881
2010-05-27 20:17:28 +00:00
Dan Gohman
bf1e648394 Simplify raw_ostream usage.
llvm-svn: 104874
2010-05-27 19:48:08 +00:00
Dan Gohman
3a54acdc12 Minor code simplification.
llvm-svn: 104845
2010-05-27 16:25:05 +00:00
Daniel Dunbar
0d29870989 AsmMatcher: Ensure classes are totally ordered, so we can std::sort them reliably.
llvm-svn: 104806
2010-05-27 05:31:32 +00:00
Jakob Stoklund Olesen
ee3ac9b299 Check that inherited subregisters all have a direct SubRegIndex.
llvm-svn: 104755
2010-05-26 22:15:07 +00:00
Jakob Stoklund Olesen
1c0aa5f14a Add StringRef::compare_numeric and use it to sort TableGen register records.
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
2010-05-26 21:47:28 +00:00
Jakob Stoklund Olesen
bf22a695bd Suppress emmission of empty subreg/superreg/alias sets.
llvm-svn: 104741
2010-05-26 21:35:55 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.

llvm-svn: 104660
2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
41388819f1 Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
llvm-svn: 104650
2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
9210d3b189 Print symbolic SubRegIndex names on machine operands.
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
6e7961be11 Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615
2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
Chris Lattner
6ea2f4d4cc diaggroup categories should take precedence over diag-specific groups.
llvm-svn: 104567
2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
2010-05-24 14:48:12 +00:00
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
Daniel Dunbar
64807873ec tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

llvm-svn: 104270
2010-05-20 20:20:32 +00:00
Daniel Dunbar
1c27a3b79d lit: Add another place to look for bash.
llvm-svn: 104189
2010-05-19 23:56:09 +00:00
Alexis Hunt
0774d14741 Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro
Also rename ABSTRACT to ABSTRACT_STMT

llvm-svn: 104018
2010-05-18 06:22:50 +00:00
Evan Cheng
2af2c9fa14 Added a QQQQ register file to model 4-consecutive Q registers.
llvm-svn: 103760
2010-05-14 02:13:41 +00:00
Evan Cheng
775549c9e7 Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
llvm-svn: 103746
2010-05-13 23:55:47 +00:00
Chandler Carruth
d37bcf5e2c Update tablegen to generate shorts instead of chars for subgroup arrays.
llvm-svn: 103704
2010-05-13 07:43:47 +00:00
Daniel Dunbar
8578537b17 lit: Fix a sh lexing bug which caused annotate-token.m to fail when run with the
internal shell parser; we weren't lexing the quotes in a command like::

  clang -DFOO='hello'

correctly.

llvm-svn: 103652
2010-05-12 21:47:58 +00:00
Daniel Dunbar
8c1208781d lit: Fix OneCommandPerFileTest format when tests are specified directly.
llvm-svn: 103626
2010-05-12 17:56:44 +00:00
Daniel Dunbar
cab93afa90 lit: Add support for 'lit ... @foo', which reads a list of tests to run from
foo.

llvm-svn: 103625
2010-05-12 17:56:42 +00:00
Dan Gohman
03e407ed83 Add initial kill flag support to FastISel.
llvm-svn: 103529
2010-05-11 23:54:07 +00:00
Douglas Gregor
2f2491405a Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!
llvm-svn: 103457
2010-05-11 06:17:44 +00:00
Sean Callanan
4331428e24 Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
2010-05-06 20:59:00 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.

llvm-svn: 103194
2010-05-06 20:33:48 +00:00
Evan Cheng
4c3022f869 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
llvm-svn: 103172
2010-05-06 06:36:08 +00:00
Alexis Hunt
24902a84b1 Fix some stylistic issues with my last commit.
llvm-svn: 103164
2010-05-06 05:24:38 +00:00
Bob Wilson
5ee6d0b151 Select an ARM-hosted cross build with a separate makefile target instead of
a magic project name.

llvm-svn: 103125
2010-05-05 22:22:40 +00:00
Jeffrey Yasskin
421cf94ea0 Rearrange the suppressions files to be by-architecture instead of by-problem.
ddunbar says the gcc-4.3.3 suppressions are obsolete.

llvm-svn: 103106
2010-05-05 18:39:16 +00:00
Jeffrey Yasskin
be201cecc8 Add a suppressions file for an intermittent "leak" under RegisterPass.
llvm-svn: 103100
2010-05-05 18:15:26 +00:00
Daniel Dunbar
772b9002e7 lit: Allow test_format to be None.
llvm-svn: 103091
2010-05-05 17:22:35 +00:00
Shantonu Sen
7e52958e05 Add newline to end of file to avoid warning
when building llvm with clang

llvm-svn: 103084
2010-05-05 13:56:46 +00:00
Alexis Hunt
f4d5520f79 Include the right header for toupper
llvm-svn: 103073
2010-05-05 04:31:44 +00:00
Alexis Hunt
55ae7d6b53 Add an emitter to handle the list of clang statement nodes.
llvm-svn: 103071
2010-05-05 04:13:08 +00:00
Chris Lattner
7b17b0d5fb add the ability to associate 'category' names with clang diagnostics
and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.

llvm-svn: 103050
2010-05-04 20:44:23 +00:00
Daniel Dunbar
711d2427dd MC/Matcher: Add support for over-riding the default MatchInstruction function
name (for example, to allow targets to interpose the actual MatchInstruction
function).

llvm-svn: 102987
2010-05-04 00:33:13 +00:00
Dan Gohman
cc176c4b1f Add a polygen rule that reflects the fact that nsw and nuw can be
used together in either order.

llvm-svn: 102983
2010-05-04 00:13:24 +00:00
Bob Wilson
5010005c87 Remove special case for llvmCore_Embedded project. This is no longer needed
since llvmCore is built as part of llvmgcc42 now.

llvm-svn: 102962
2010-05-03 21:41:24 +00:00
Evan Cheng
8bd004b033 Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026

llvm-svn: 102815
2010-05-01 00:28:44 +00:00
Bob Wilson
1576577ead Don't remove libLTO.dylib if it's not being installed in Developer/usr/lib;
just leave it in Developer/usr/local/lib.

llvm-svn: 102646
2010-04-29 18:04:29 +00:00
Bob Wilson
ed156c2212 Add an option to the Apple-style build to control whether libLTO.dylib should
be installed.  Disable it by default.

llvm-svn: 102531
2010-04-28 21:08:01 +00:00
Bob Wilson
98f2186636 Undo most of my previous whitespace fix. I think I like it better this way
after all.

llvm-svn: 102508
2010-04-28 18:18:36 +00:00
Bob Wilson
ba5b622a80 Fix inconsistent use of HOSTS and TARGETS variables.
llvm-svn: 102505
2010-04-28 18:06:27 +00:00
Bob Wilson
07f7b3462e Fix whitespace.
llvm-svn: 102504
2010-04-28 17:50:03 +00:00
Sean Callanan
72d3d36188 Fixes to edis that mark x86 call targets as
memory operands rather than immediate operands.

llvm-svn: 102217
2010-04-23 22:17:17 +00:00
Johnny Chen
9998480f92 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929
2010-04-20 18:45:24 +00:00
Chris Lattner
6a517dbbd6 stop computing InstImpInputs, it is dead
llvm-svn: 101881
2010-04-20 06:30:25 +00:00
Chris Lattner
8b5bae8c3c DAGInstruction::ImpOperands is dead after my recent tblgen work, zap it.
llvm-svn: 101880
2010-04-20 06:28:43 +00:00
Anton Korobeynikov
e325c693a5 Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
2010-04-18 20:31:01 +00:00
Chris Lattner
9d12c8bb70 silence some -Wmissing-field-initializers warnings.
llvm-svn: 101690
2010-04-18 03:30:32 +00:00
Dan Gohman
d48633d340 Fix a bunch of namespace polution.
llvm-svn: 101376
2010-04-15 17:08:50 +00:00
Daniel Dunbar
3bf3e0e63a Remove unnecessary uses of <iostream>.
llvm-svn: 101338
2010-04-15 03:47:24 +00:00
Benjamin Kramer
84265367be EDis: Don't include inttypes.h. We support compilers which don't provide it. It was unused anyways.
llvm-svn: 101241
2010-04-14 13:56:38 +00:00
Daniel Dunbar
d3c1f99fa1 Fix -Asserts warnings.
llvm-svn: 101191
2010-04-13 23:34:11 +00:00
Sean Callanan
29a7152676 Fixed a nasty layering violation in the edis source
code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.

llvm-svn: 101179
2010-04-13 21:21:57 +00:00
Johnny Chen
b6b7028930 If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.

llvm-svn: 100899
2010-04-09 21:01:02 +00:00
Chris Lattner
9d77e5ba47 add minix support, patch by Kees van Reeuwijk! PR6797
llvm-svn: 100895
2010-04-09 20:45:04 +00:00
Bob Wilson
ef934eac9f Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.

llvm-svn: 100892
2010-04-09 20:41:18 +00:00
Johnny Chen
c531a30631 ARM decoder emitter should print out useful information unconditionally when it
encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. 

llvm-svn: 100886
2010-04-09 19:31:33 +00:00
Daniel Dunbar
4ddbf8ad2c lit: Add support to OneCommandPerFileTest format to take input directory from input path.
llvm-svn: 100846
2010-04-09 02:15:10 +00:00
Johnny Chen
43b072e18d Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround code
to avoid memcpy() call is no longer necessary.

llvm-svn: 100811
2010-04-08 21:23:54 +00:00
Benjamin Kramer
3b7602b1fb Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.
llvm-svn: 100767
2010-04-08 15:25:57 +00:00
Benjamin Kramer
f0ecbf7c5d Use errs instead of fprintf.
llvm-svn: 100754
2010-04-08 09:42:29 +00:00
Sean Callanan
dcd7a375dd Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

llvm-svn: 100735
2010-04-08 00:48:21 +00:00
Chris Lattner
80b41881bc rename llvm::llvm_report_error -> llvm::report_fatal_error
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Chris Lattner
a58082f349 add newlines at end of files.
llvm-svn: 100706
2010-04-07 22:54:55 +00:00
Sean Callanan
3c69c6593a Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694
2010-04-07 21:42:19 +00:00
Eric Christopher
0b9a4cb3d7 Fix typo and correct comment somewhat.
llvm-svn: 100691
2010-04-07 20:58:16 +00:00
Johnny Chen
2c992fb384 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690
2010-04-07 20:53:12 +00:00
Anton Korobeynikov
f93145e685 Initial support for different kinds of FU reservation.
llvm-svn: 100645
2010-04-07 18:19:32 +00:00
Chris Lattner
269737461d stringref-ize the MemoryBuffer::get apis. This requires
a co-committed clang patch.

llvm-svn: 100485
2010-04-05 22:42:30 +00:00
Jakob Stoklund Olesen
4c043c50fd Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
2010-04-05 03:10:20 +00:00
Chris Lattner
cdbca3e8fe change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter.  Instead, pass it in explicitly.

llvm-svn: 100306
2010-04-04 04:47:45 +00:00
Chandler Carruth
6d6f54a390 Fix a warning in GCC about a pointless typedef.
llvm-svn: 100268
2010-04-03 04:45:24 +00:00
Chandler Carruth
c6c39a6380 Add the new ARMDecodeEmitter to CMake build.
llvm-svn: 100267
2010-04-03 04:36:43 +00:00
Johnny Chen
62e8d73827 Move variable "Bits" declaration/definition into the DEBUG block where its usage
is expected.

llvm-svn: 100247
2010-04-02 23:13:52 +00:00
Johnny Chen
35c2015164 Fixed build warning.
llvm-svn: 100244
2010-04-02 22:51:04 +00:00
Johnny Chen
9b11d5b81a Change from .../Support/DataTypes.h to .../System/DataTypes.h.
(Fix build failure)

llvm-svn: 100243
2010-04-02 22:41:06 +00:00
Johnny Chen
6d9cbe7270 Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233
2010-04-02 22:27:38 +00:00
Daniel Dunbar
1a27d28404 Add a FIXME.
llvm-svn: 100034
2010-03-31 19:14:05 +00:00
Daniel Dunbar
9c71d03e49 lit: Make sure to close any files we open as part of redirection.
PR6753.

llvm-svn: 100032
2010-03-31 18:48:43 +00:00
Chris Lattner
01d6e19c75 Switch pattern sorting predicate from stable sort -> sort, it
doesn't need to be stable because the patterns are fully ordered.

Add a first level sort predicate that orders patterns in this
order:  1) scalar integer operations 2) scalar floating point 
3) vector int 4) vector float.  This is a trivial sort on their
top level pattern type so it is nice and transitive.  The
benefit of doing this is that simple integer operations are
much more common than insane vector things and isel was trying
to match the big complex vector patterns before the simple
ones because the complexity of the vector operations was much
higher.  Since they can't both match, it is best (for compile
time) to try the simple integer ones first.

This cuts down the # failed match attempts on real code by
quite a bit, for example, this reduces backtracks on crafty
(as a random example) from 228285 -> 188369.

llvm-svn: 99797
2010-03-29 02:02:45 +00:00
Chris Lattner
6129cf2814 revert 99795, as mentioned, it is disabled anyway.
llvm-svn: 99796
2010-03-29 01:58:15 +00:00
Chris Lattner
8535a74712 Check in a (disabled) failed attempt to improve the ordering of
patterns within the generated matcher.  This works great except
that the sort fails because the relation defined isn't 
transitive.  I have a much simpler solution coming next, but want
to archive the code.

llvm-svn: 99795
2010-03-29 01:56:19 +00:00
Chris Lattner
3bb37074fd print the complexity of the pattern being matched in the
comment in the generated table.

llvm-svn: 99794
2010-03-29 01:40:38 +00:00
Chris Lattner
117eb269f9 improve type checking of SDNode operand count. This rejects all cases
where an incorrect number of operands is provided to an sdnode instead
of just a few cases.

llvm-svn: 99761
2010-03-28 08:48:47 +00:00
Chris Lattner
5ad69fe4b6 finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)

llvm-svn: 99759
2010-03-28 08:43:23 +00:00
Chris Lattner
e04fb0a1a7 teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4),
transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.

llvm-svn: 99756
2010-03-28 08:38:32 +00:00
Chris Lattner
af75e6a61f validate that input sdnodes don't exist in an output pattern.
llvm-svn: 99747
2010-03-28 06:57:56 +00:00
Chris Lattner
5bb82e570e eliminate a bunch of code duplication in ParseTreePattern
by rotating it.

llvm-svn: 99746
2010-03-28 06:50:34 +00:00
Chris Lattner
7c35e259aa SDTCisVT<0, isVoid> is not valid, reject it.
llvm-svn: 99744
2010-03-28 06:04:39 +00:00
Chris Lattner
3f060e3216 add an optimized form of OPC_EmitMergeInputChains for the 1, 0 and
1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.

llvm-svn: 99740
2010-03-28 05:50:16 +00:00
Chris Lattner
70189ff5ab fix a long standing fixme, which required fixing a bunch of other
issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.

llvm-svn: 99728
2010-03-27 20:45:15 +00:00
Chris Lattner
d6afc9e48d fix CodeGenTarget::getRegisterVTs to not return the
same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.

llvm-svn: 99727
2010-03-27 20:32:26 +00:00
Chris Lattner
2ec88c02da hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.

llvm-svn: 99726
2010-03-27 20:09:24 +00:00
Chris Lattner
ad983d7a8a continue pushing tblgen's support for nodes with multiple
results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.

llvm-svn: 99725
2010-03-27 19:15:02 +00:00
Chris Lattner
30f1286d4c fix a bug in my recent patch that increased opcode size to 2 bytes:
the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.

llvm-svn: 99722
2010-03-27 18:49:33 +00:00
Dan Gohman
f8a50c52df Remove an unnecessary #include.
llvm-svn: 99714
2010-03-27 16:33:36 +00:00
Chris Lattner
d2dd416772 remove parallel support.
llvm-svn: 99703
2010-03-27 02:53:27 +00:00
Jakob Stoklund Olesen
5a6e614de9 Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539
2010-03-25 18:52:01 +00:00
Daniel Dunbar
6de90fba7e lit: Add LitTestCase and lit.load_test_suite, for adapting lit based suites for
use with Python's unittest.

llvm-svn: 99498
2010-03-25 07:10:01 +00:00
Chris Lattner
13f444cdf1 Change tblgen to emit FOOISD opcode names as two
bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648

llvm-svn: 99494
2010-03-25 06:33:05 +00:00
Jakob Stoklund Olesen
85e615223f Fix evil TableGen bug in template parameters with defaults.
If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.

llvm-svn: 99492
2010-03-25 06:23:34 +00:00
Chris Lattner
cb2f61f245 add plumbing for handling multiple result nodes
in some more places.

llvm-svn: 99366
2010-03-24 00:41:19 +00:00
Chris Lattner
01e2cd0da3 implement SDTCisVTSmallerThanOp with EnforceSmallerThan
instead of reimplementing it wrong and poorly.

llvm-svn: 99357
2010-03-24 00:06:46 +00:00
Chris Lattner
292d6c4f7e bring sanity to EnforceVectorEltType
llvm-svn: 99354
2010-03-24 00:01:16 +00:00
Chris Lattner
d0c16ce3c3 Cleanup getImplicitType
llvm-svn: 99353
2010-03-23 23:50:31 +00:00
Chris Lattner
a682c112da reject void in intrinsic type lists.
llvm-svn: 99347
2010-03-23 23:46:27 +00:00
Bill Wendling
9a977ce8ce Use "DISABLE_EDIS" to disable building "edis" explicitly. Don't build it for
Apple-style builds.

llvm-svn: 99336
2010-03-23 22:15:33 +00:00
Chris Lattner
c4be1194e5 Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.  Now with a fix
for the verifier.

llvm-svn: 99206
2010-03-22 20:56:36 +00:00
Jeffrey Yasskin
28c789b8a6 When we don't pass --vg-leak to lit, pass --leak-check=no to valgrind.
llvm-svn: 99112
2010-03-21 01:47:33 +00:00
Daniel Dunbar
575d014f60 Fix suggested parentheses warning.
llvm-svn: 99111
2010-03-21 01:38:21 +00:00
Jeffrey Yasskin
4927fd0032 Add support for XFAILing valgrind runs with memory leak checking independently
of runs without leak checking.  We add -vg to the triple for non-checked runs,
or -vg_leak for checked runs.  Also use this to XFAIL the TableGen tests, since
tablegen leaks like a sieve.  This includes some valgrindArgs refactoring.

llvm-svn: 99103
2010-03-20 23:08:45 +00:00
Eric Christopher
b41284cea9 Revert r99009 temporarily it seems to be breaking the bots.
llvm-svn: 99011
2010-03-19 23:04:23 +00:00
Chris Lattner
4af1cae2f1 Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.

llvm-svn: 99009
2010-03-19 22:40:56 +00:00
Chris Lattner
eb5e201050 make getOperandNum a static function (since it's just used by
ApplyTypeConstraint) and make it handle multiple result nodes.

llvm-svn: 99003
2010-03-19 21:56:21 +00:00
Chris Lattner
e425c6ab6c major surgery on tblgen: generalize TreePatternNode
to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.

llvm-svn: 98999
2010-03-19 21:37:09 +00:00
Ben Holt
fa824e3279 Test commit (removed extra blank line)
llvm-svn: 98988
2010-03-19 21:12:29 +00:00
Daniel Dunbar
41e0c40cf4 FileCheck: Don't print "possibly intended match" line if it would match the
"scanning from here" one.

llvm-svn: 98971
2010-03-19 18:07:43 +00:00
Torok Edwin
ec792738a5 Set numThreads to 1 by default when Python is older than 2.5.2.
Python 2.4 always hits this bug: http://bugs.python.org/issue1731717
when running check-lit on multi-core systems.
Setting numThreads to 1 makes it slower, but at least the results reported are
correct.

llvm-svn: 98969
2010-03-19 17:54:21 +00:00
Chris Lattner
5d1378e7a3 make FillWithPossibleTypes take a predicate to filter types so that
we don't blow the smallvector as often.  No functionality change.

llvm-svn: 98968
2010-03-19 17:41:26 +00:00
Chris Lattner
5afb55e172 resolve fixme: we now infer the instruction-level 'isvariadic' bit
from the pattern if present, and we use it instead of the bit.

llvm-svn: 98938
2010-03-19 05:34:15 +00:00
Chris Lattner
6b395fca87 add a new SDNPVariadic SDNP node flag, and use it in
dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934
2010-03-19 05:07:09 +00:00
Chris Lattner
0f1c18d7e6 rewrite EnforceSmallerThan to be less bone headed.
llvm-svn: 98933
2010-03-19 04:54:36 +00:00
Daniel Dunbar
cc34ff9e80 Fix -Asserts warning.
llvm-svn: 98927
2010-03-19 03:18:20 +00:00
Chris Lattner
68762f16c5 eliminate the last use of EEVT::isUnknown
llvm-svn: 98918
2010-03-19 01:14:27 +00:00
Chris Lattner
4950930fa7 Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).

llvm-svn: 98916
2010-03-19 01:07:44 +00:00
Chris Lattner
3f22bdc032 make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.

llvm-svn: 98915
2010-03-19 01:00:55 +00:00
Chris Lattner
42d67226c5 revert 98912
llvm-svn: 98914
2010-03-19 00:50:47 +00:00
Chris Lattner
f0beb5287b make inst_begin/inst_end iterate over InstructionsByEnumValue.
llvm-svn: 98912
2010-03-19 00:40:22 +00:00
Chris Lattner
b929ca1352 change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910
2010-03-19 00:34:35 +00:00
Chris Lattner
cef8991a14 factor copy and paste code.
llvm-svn: 98908
2010-03-19 00:23:20 +00:00
Chris Lattner
1acf5e4a8d don't go through getInstructions().
llvm-svn: 98906
2010-03-19 00:18:23 +00:00
Chris Lattner
3e5af02a79 look up instructions by record, not by name.
llvm-svn: 98904
2010-03-19 00:07:20 +00:00
Chris Lattner
0ed7a372d6 expand tblgen's support for instructions with implicit defs.
llvm-svn: 98900
2010-03-18 23:57:40 +00:00
Chris Lattner
5becdf478d infer results of a pattern from implicit defs. This allows you to do something
like this:

 def : Pat<(add ...),
           (FOOINST)>;

When fooinst only has a single implicit def (e.g. to R1).  This will be handled
as if written as (set R1, (FOOINST ...))

llvm-svn: 98897
2010-03-18 23:15:10 +00:00
Chris Lattner
1bc6faaac4 capture implicit uses and defs in CodeGenInstruction
llvm-svn: 98879
2010-03-18 21:42:03 +00:00
Chris Lattner
fa01855463 simplify this code, the # of sets in the pattern for an instruction
shouldn't change this.

llvm-svn: 98872
2010-03-18 21:15:05 +00:00
Chris Lattner
918789d239 disallow concatenation of two dags with different operators.
llvm-svn: 98871
2010-03-18 21:07:51 +00:00
Chris Lattner
ee0d794686 rewrite this to not artificially force concat the ins/outs list.
llvm-svn: 98870
2010-03-18 21:07:39 +00:00
Chris Lattner
48330afb2d eliminate support for "ops" in the input/output list of an
instruction.  Instructions must use 'ins' and 'outs' now.

llvm-svn: 98868
2010-03-18 20:56:35 +00:00
Chris Lattner
3f7819560f remove some code that was working around old sparc v9 backend bugs.
Add checking that the input/output operand list in spelled right.

llvm-svn: 98865
2010-03-18 20:50:52 +00:00
Daniel Dunbar
d655f05fb9 lit: Tweak example tests config.
llvm-svn: 98859
2010-03-18 20:06:05 +00:00
Daniel Dunbar
571a3eb0b6 MC/AsmMatcher: Add support for target specific "instruction cleanup" functions,
to allow custom post-processing of matched instructions.

llvm-svn: 98857
2010-03-18 20:05:56 +00:00