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Author SHA1 Message Date
Jim Grosbach
a0f673b561 Add MOVi ARM encoding. 
llvm-svn: 116321
 2010-10-12 18:09:12 +00:00
Dan Gohman
d904add908 Initial va_arg support for x86-64. Patch by David Meyer! 
llvm-svn: 116319
 2010-10-12 18:00:49 +00:00
Jim Grosbach
dbf116be66 Nuke unused wrapper function. 
llvm-svn: 116318
 2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
499fe39d23 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314
 2010-10-12 17:15:00 +00:00
Jim Grosbach
10d9bbe0ca Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

llvm-svn: 116313
 2010-10-12 17:11:26 +00:00
Bob Wilson
bbb91c6a1c PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310
 2010-10-12 16:22:47 +00:00
Eric Christopher
0763cc04c5 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher
8a4621b7df Fix the last two commits to configure - configure is a generated file. 
Made necessary edits to configure.ac and regenerated.

llvm-svn: 116291
 2010-10-12 02:42:05 +00:00
Eric Christopher
8789aa8799 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Cameron Esfahani
71cdbd5d44 Fix spelling error. 
llvm-svn: 116282
 2010-10-12 00:21:05 +00:00
Dan Gohman
d1789c3cef Delete a redundant check. 
llvm-svn: 116280
 2010-10-12 00:19:24 +00:00
Dan Gohman
3b55a1294e More SmallVectorImpls. 
llvm-svn: 116279
 2010-10-12 00:15:27 +00:00
Dan Gohman
cca2c82199 Shrink a SmallVector with a known maximum size. 
llvm-svn: 116278
 2010-10-12 00:13:43 +00:00
Dan Gohman
c49d367fb9 Constify. 
llvm-svn: 116277
 2010-10-12 00:12:29 +00:00
Dan Gohman
dbb5a62aba Use SmallVectorImpl in a bunch of places. 
llvm-svn: 116276
 2010-10-12 00:11:18 +00:00
Francois Pichet
6bf8a81c52 Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64. 
llvm-svn: 116274
 2010-10-12 00:01:36 +00:00
Dan Gohman
8dc9781a91 Add a simple testcase for tbaa. 
llvm-svn: 116272
 2010-10-11 23:54:13 +00:00
Evan Cheng
6aac1548ab More ARM scheduling itinerary fixes. 
llvm-svn: 116266
 2010-10-11 23:41:41 +00:00
Dan Gohman
4231230501 Support AA chaining. 
llvm-svn: 116264
 2010-10-11 23:39:34 +00:00
Dan Gohman
3d1fa9f524 Fix the pass manager's search order for immutable passes, and make it 
stop searching when it has found a match.

llvm-svn: 116262
 2010-10-11 23:19:01 +00:00
Jim Grosbach
29ef87e765 MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

llvm-svn: 116259
 2010-10-11 23:16:21 +00:00
Jason W Kim
59375bae75 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257
 2010-10-11 23:01:44 +00:00
Dan Gohman
68f316a93c Clang's #include handling apparently doesn't work for libstdc++'s 
fenv.h. See PR6907 for details. Work around this in FEnv.h to fix
the seflhost build.

llvm-svn: 116256
 2010-10-11 22:30:59 +00:00
Michael J. Spencer
6b47972a41 Unit Tests: Missed this error. MSVC and clang didn't complain. 
llvm-svn: 116252
 2010-10-11 22:04:38 +00:00
Evan Cheng
77ba7b098a Proper VST scheduling itineraries. 
llvm-svn: 116251
 2010-10-11 22:03:18 +00:00
Eric Christopher
e1574aa60a Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Michael J. Spencer
0888ccaa19 System: Add SwapByteOrder and update Support/MathExtras.h to use it. 
This time correctly.

llvm-svn: 116247
 2010-10-11 21:56:16 +00:00
Jakob Stoklund Olesen
44943ef3f8 Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis. 
This helps hiding the LiveRange class which really should be private.

llvm-svn: 116244
 2010-10-11 21:45:03 +00:00
Jim Grosbach
06a0fb7aff The assert() should reference to machine instr operand number, too. 
llvm-svn: 116243
 2010-10-11 21:41:31 +00:00
Michael J. Spencer
0af3659b5d Revert "System: Add SwapByteOrder and update Support/MathExtras.h to use it." 
This reverts commit 116234.

It compiled just fine with MSVC and clang...

llvm-svn: 116242
 2010-10-11 21:39:24 +00:00
Eric Christopher
926a41a84b We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Daniel Dunbar
2b6bcb4978 Change explicit search Apple specific code to only reference __eprintf on x86. 
llvm-svn: 116239
 2010-10-11 21:34:24 +00:00
Jim Grosbach
bfc337878b Make sure to use the machine instruction operand number. It doesn't always 
map one-to-one with the CodeGenInstruction operand number.

llvm-svn: 116238
 2010-10-11 21:31:22 +00:00
Michael J. Spencer
29e2ba9ca8 Reduce dpendencies for SupportTests. 
llvm-svn: 116235
 2010-10-11 21:22:34 +00:00
Michael J. Spencer
d0d6c9b01e System: Add SwapByteOrder and update Support/MathExtras.h to use it. 
llvm-svn: 116234
 2010-10-11 21:22:22 +00:00
Eric Christopher
cac7b248c7 Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
 2010-10-11 21:20:02 +00:00
Andrew Trick
5361f35978 PR8297 
llvm-svn: 116223
 2010-10-11 21:08:42 +00:00
Jakob Stoklund Olesen
a0a5015a35 PowerPC varargs functions store live-in registers on the stack. Make sure we use 
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

llvm-svn: 116222
 2010-10-11 20:43:09 +00:00
Eric Christopher
fa961e31b1 Found a bug turning this on by default. Disable again for now. 
llvm-svn: 116220
 2010-10-11 20:26:21 +00:00
Eric Christopher
b477aa7c6f Remove now non-existent option. 
llvm-svn: 116219
 2010-10-11 20:21:21 +00:00
Eric Christopher
ff35a1f090 Fix help text. 
llvm-svn: 116218
 2010-10-11 20:15:02 +00:00
Eric Christopher
b1a93706f7 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
 2010-10-11 20:05:22 +00:00
Michael J. Spencer
39ce18d108 Add KillTheDoctor. 
llvm-svn: 116216
 2010-10-11 19:55:38 +00:00
Jim Grosbach
eded540b87 trailing whitespace cleanup 
llvm-svn: 116215
 2010-10-11 19:38:01 +00:00
Andrew Trick
5704a15e36 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand 
llvm-svn: 116214
 2010-10-11 19:02:04 +00:00
Jim Grosbach
a697e32f36 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.

llvm-svn: 116213
 2010-10-11 18:51:51 +00:00
Eric Christopher
52c102fef0 Turn on arm fast isel by default. 
llvm-svn: 116212
 2010-10-11 18:48:18 +00:00
Jim Grosbach
8fae045502 When figuring out which operands match which encoding fields in an instruction, 
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).

llvm-svn: 116211
 2010-10-11 18:25:51 +00:00
Jakob Stoklund Olesen
ecf3e62010 Properly handle reloading and spilling around partial redefines in 
LocalRewriter.

This is a bit of a hack that adds an implicit use operand to model the
read-modify-write nature of a partial redef. Uses and defs are rewritten in
separate passes, and a single operand would never be processed twice.

<rdar://problem/8518892>

llvm-svn: 116210
 2010-10-11 18:10:36 +00:00
Chris Lattner
d60c4c8a13 remove dead prototype, PR8351 
llvm-svn: 116209
 2010-10-11 17:44:22 +00:00