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Author SHA1 Message Date
Chris Lattner
dc8e8484e5 Second half of my fixed-sized-alloca patch. This folds the LEA to compute 
the alloca address into common operations like loads/stores.

In a simple testcase like this (which is just designed to excersize the
alloca A, nothing more):

int %test(int %X, bool %C) {
        %A = alloca int
        store int %X, int* %A
        store int* %A, int** %G
        br bool %C, label %T, label %F
T:
        call int %test(int 1, bool false)
        %V = load int* %A
        ret int %V
F:
        call int %test(int 123, bool true)
        %V2 = load int* %A
        ret int %V2
}

We now generate:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %CL, BYTE PTR [%ESP + 20]
***     mov DWORD PTR [%ESP + 8], %EAX
        mov %EAX, OFFSET G
        lea %EDX, DWORD PTR [%ESP + 8]
        mov DWORD PTR [%EAX], %EDX
        test %CL, %CL
        je .LBB2 # PC rel: F
.LBB1:  # T
        mov DWORD PTR [%ESP], 1
        mov DWORD PTR [%ESP + 4], 0
        call test
***     mov %EAX, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret
.LBB2:  # F
        mov DWORD PTR [%ESP], 123
        mov DWORD PTR [%ESP + 4], 1
        call test
***     mov %EAX, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret

Instead of:

test:
        sub %ESP, 20
        mov %EAX, DWORD PTR [%ESP + 24]
        mov %CL, BYTE PTR [%ESP + 28]
***     lea %EDX, DWORD PTR [%ESP + 16]
***     mov DWORD PTR [%EDX], %EAX
        mov %EAX, OFFSET G
        mov DWORD PTR [%EAX], %EDX
        test %CL, %CL
***     mov DWORD PTR [%ESP + 12], %EDX
        je .LBB2 # PC rel: F
.LBB1:  # T
        mov DWORD PTR [%ESP], 1
        mov %EAX, 0
        mov DWORD PTR [%ESP + 4], %EAX
        call test
***     mov %EAX, DWORD PTR [%ESP + 12]
***     mov %EAX, DWORD PTR [%EAX]
        add %ESP, 20
        ret
.LBB2:  # F
        mov DWORD PTR [%ESP], 123
        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX
        call test
***     mov %EAX, DWORD PTR [%ESP + 12]
***     mov %EAX, DWORD PTR [%EAX]
        add %ESP, 20
        ret

llvm-svn: 13557
 2004-05-13 15:12:43 +00:00
Chris Lattner
94de563118 Substantially improve code generation for address exposed locals (aka fixed 
sized allocas in the entry block).  Instead of generating code like this:

entry:
  reg1024 = ESP+1234
... (much later)
  *reg1024 = 17


Generate code that looks like this:
entry:
  (no code generated)
... (much later)
  t = ESP+1234
  *t = 17

The advantage being that we DRAMATICALLY reduce the register pressure for these
silly temporaries (they were all being spilled to the stack, resulting in very
silly code).  This is actually a manual implementation of rematerialization :)

I have a patch to fold the alloca address computation into loads & stores, which
will make this much better still, but just getting this right took way too much time
and I'm sleepy.

llvm-svn: 13554
 2004-05-13 07:40:27 +00:00
Chris Lattner
a19bb14155 Pass boolean constants into function calls more efficiently, generating: 
mov DWORD PTR [%ESP + 4], 1

instead of:

        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX

llvm-svn: 13494
 2004-05-12 16:35:04 +00:00
Chris Lattner
a407338e12 Fix a fairly serious pessimizaion that was preventing us from efficiently 
compiling things like 'add long %X, 1'.  The problem is that we were switching
the order of the operands for longs even though we can't fold them yet.

llvm-svn: 13451
 2004-05-10 15:15:55 +00:00
Chris Lattner
0962db8f10 Fix some comments, avoid sign extending booleans when zero extend works fine 
llvm-svn: 13440
 2004-05-09 23:16:33 +00:00
Chris Lattner
d18c637a37 Generate more efficient code for casting booleans to integers (no sign extension required) 
llvm-svn: 13439
 2004-05-09 22:28:45 +00:00
Chris Lattner
8ccfc21a0f syntactically loopify natural loops so that the GCC loop optimizer can find them. This should *dramatically* improve the performance of CBE compiled code on targets that depend on GCC's loop optimizations (like PPC) 
llvm-svn: 13438
 2004-05-09 20:41:32 +00:00
Chris Lattner
c6a63660e6 Do not emit prototypes for setjmp/longjmp, as they are handled specially 
llvm-svn: 13437
 2004-05-09 16:03:29 +00:00
Chris Lattner
4926af5c32 Make the floating point constant pools local to each function, split the 
FindUsedTypes manipulation stuff out to be a seperate pass, and make the
main CWriter be a function pass now!

llvm-svn: 13435
 2004-05-09 06:20:51 +00:00
Chris Lattner
37abb037bf Get this looking more like a function pass. 
llvm-svn: 13433
 2004-05-09 04:30:20 +00:00
Chris Lattner
99b7c2b532 Print all PHI copies for successor blocks before the terminator, whether it be a conditional branch or switch. 
llvm-svn: 13430
 2004-05-09 03:42:48 +00:00
Tanya Lattner
b6ecf521da Changed CPUResource to allow access to maxnum users. 
llvm-svn: 13425
 2004-05-08 16:12:50 +00:00
Brian Gaeke
7cc5d0f106 Add support for widening integral casts. 
Flesh out the SetCC support... which currently ends in a little bit
of unfinished code (which is probably completely hilarious) for
generating the condition value splitting the basic block up into 4
blocks, like this (clearly a better API is needed for this!):

       BB
   cond. branch
     /         /          R1=1    R2=0
     \      /
      \    /
    R=phi(R1,R2)

Other minor edits.

llvm-svn: 13423
 2004-05-08 06:36:14 +00:00
Brian Gaeke
58fd2b0e4a Add a bunch more branches 
llvm-svn: 13422
 2004-05-08 06:08:29 +00:00
Brian Gaeke
faf41642ca Flesh out GEP support 
llvm-svn: 13421
 2004-05-08 05:27:20 +00:00
Brian Gaeke
e44dbd4a39 Add ADD with immediate 
llvm-svn: 13420
 2004-05-08 05:26:55 +00:00
Brian Gaeke
5861a59506 Add forms of CMP, SUBCC, and a few branches, and some comments. 
llvm-svn: 13419
 2004-05-08 04:21:32 +00:00
Brian Gaeke
eaf8a021e3 Add stub support for GEPs. 
Add support for branches (based loosely on X86/InstSelectSimple).
Add support for not visiting phi nodes in the first pass.
Add support for loading bools.
Flesh out support for stores.

llvm-svn: 13418
 2004-05-08 04:21:17 +00:00
Brian Gaeke
0d477a958f Add support for copying bool constants to registers. 
Disable the code that copies long constants to registers - it looks fishy.
Implement some simple casts: integral, smaller than longs, and equal-width
 or narrowing only.

llvm-svn: 13413
 2004-05-07 21:39:30 +00:00
Chris Lattner
67c21e74ec Codegen floating point stores of constants into integer instructions. This 
allows us to compile:

store float 10.0, float* %P

into:
        mov DWORD PTR [%EAX], 1092616192

instead of:

.CPItest_0:                                     # float 0x4024000000000000
.long   1092616192      # float 10
...
        fld DWORD PTR [.CPItest_0]
        fstp DWORD PTR [%EAX]

llvm-svn: 13409
 2004-05-07 21:18:15 +00:00
Chris Lattner
2021030378 Make comparisons against the null pointer as efficient as integer comparisons 
against zero.  In particular, don't emit:

        mov %ESI, 0
        cmp %ECX, %ESI

instead, emit:

       test %ECX, %ECX

llvm-svn: 13407
 2004-05-07 19:55:55 +00:00
Brian Gaeke
c9ca9d6625 Missing piece of fix for Bug 333 
llvm-svn: 13362
 2004-05-04 21:41:45 +00:00
Brian Gaeke
28d81c4d0d Correctly mangle function names when they are used as part of a 
constant pool member's name.
This is intended to address Bug 333.

Also, fix an anachronistic usage of "M" as a parameter of type Function *.

llvm-svn: 13357
 2004-05-04 21:09:02 +00:00
Chris Lattner
42e602b94f Remove unneeded check 
llvm-svn: 13355
 2004-05-04 19:35:11 +00:00
Chris Lattner
dac54ebbee Improve signed division by power of 2 *dramatically* from this: 
div:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %ECX, 64
        mov %EAX, %EDX
        sar %EDX, 31
        idiv %ECX
        ret

to this:

div:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 5
        shr %ECX, 26
        mov %EDX, %EAX
        add %EDX, %ECX
        sar %EAX, 6
        ret

Note that the intel compiler is currently making this:

div:
        movl      4(%esp), %edx                                 #3.5
        movl      %edx, %eax                                    #4.14
        sarl      $5, %eax                                      #4.14
        shrl      $26, %eax                                     #4.14
        addl      %edx, %eax                                    #4.14
        sarl      $6, %eax                                      #4.14
        ret                                                     #4.14

Which has one less register->register copy.  (hint hint alkis :)

llvm-svn: 13354
 2004-05-04 19:33:58 +00:00
Chris Lattner
cb9a614ea4 Improve code generated for integer multiplications by 2,3,5,9 
llvm-svn: 13342
 2004-05-04 15:47:14 +00:00
Chris Lattner
4b5d4eb5b1 Remove unused #include 
llvm-svn: 13304
 2004-05-01 21:29:16 +00:00
Chris Lattner
ffbf667718 Iterate over the Machine CFG that Brian added instead of the LLVM CFG. 
Look at all of the pretty minuses. :)

llvm-svn: 13303
 2004-05-01 21:27:53 +00:00
Chris Lattner
5f29db9741 Add a constructor that got lost 
llvm-svn: 13297
 2004-05-01 11:17:13 +00:00
Tanya Lattner
077c819d5a Removing MachineResource class. 
llvm-svn: 13291
 2004-04-30 20:40:38 +00:00
Brian Gaeke
bfb4fe5109 Make RequiresFPRegKill() take a MachineBasicBlock arg. 
In InsertFPRegKills(), just check the MachineBasicBlock for successors
instead of its corresponding BasicBlock.

llvm-svn: 13213
 2004-04-28 04:45:55 +00:00
Brian Gaeke
74ed24c9de In InsertFPRegKills(), use the machine-CFG itself rather than the 
LLVM CFG when trying to find the successors of BB.

llvm-svn: 13212
 2004-04-28 04:34:16 +00:00
Brian Gaeke
6c03805717 Update the machine-CFG edges whenever we see a branch. 
llvm-svn: 13211
 2004-04-28 04:19:37 +00:00
Brian Gaeke
7ce5ef244a Integrate the rest of my random sparcv9 scribblings into this file 
llvm-svn: 13204
 2004-04-27 22:04:03 +00:00
Chris Lattner
02c65b5395 Changes to fix up the inst_iterator to pass to boost iterator checks. This 
patch was graciously contributed by Vladimir Prus.

llvm-svn: 13185
 2004-04-27 15:13:33 +00:00
Brian Gaeke
1e049bdc77 Fix file header comments and include guards -- many files have been moved or 
renamed since they were last spiffed up, or they just never had proper comments
in the first place.

llvm-svn: 13148
 2004-04-25 07:04:49 +00:00
Brian Gaeke
c3857275f9 Add a getRegisterInfo() accessor just like on the X86 target. 
llvm-svn: 13147
 2004-04-25 06:32:28 +00:00
Brian Gaeke
6e21a0858c Regularize file header comment and include guard. 
Include SparcV9RegisterInfo.h.
Add a getRegisterInfo() accessor and SparcV9RegisterInfo instance, just like
on the X86 target.

llvm-svn: 13146
 2004-04-25 06:32:16 +00:00
Brian Gaeke
a36743c473 Add MRegisterInfo subclass for the SparcV9 target (containing only stub 
functions for now). This automatically turns on the printing of machine
registers using their own real names, instead of goofy things like %mreg(42),
and allows us to migrate code incrementally to the new interface as we see fit.

The register file description it uses is hand-written, so that the register
numbers will match the ones that the SparcV9 target already uses.
Perhaps someday we'll tablegen it.

llvm-svn: 13145
 2004-04-25 06:32:05 +00:00
Brian Gaeke
6ed3b116bc Fix a typo. 
llvm-svn: 13136
 2004-04-23 21:45:02 +00:00
Brian Gaeke
7fba37bb96 Merge TargetRegInfo.h into SparcV9RegInfo.h, which is its only subclass. 
This prepares us to be able to de-virtualize and de-abstract it, and
take the register allocator bits out and move them into the register allocator
proper...

llvm-svn: 13127
 2004-04-23 18:15:48 +00:00
Brian Gaeke
40c7e110a5 Include SparcV9RegInfo.h instead of TargetRegInfo.h. 
llvm-svn: 13126
 2004-04-23 18:15:47 +00:00
Brian Gaeke
07344c1367 Get rid of the old byte-at-a-time emission code used when the Sparc JIT was 
being tested on X86, as per Chris's request.

llvm-svn: 13124
 2004-04-23 18:10:38 +00:00
Brian Gaeke
0db103b4b3 Use emitWordAt() to emit forward-branch fixups. 
llvm-svn: 13120
 2004-04-23 17:11:16 +00:00
Brian Gaeke
255d0d9b26 Emit SPARC machine code a word at a time instead of a byte at a time. 
Use emitWordAt() to emit forward-branch fixups.

llvm-svn: 13119
 2004-04-23 17:11:15 +00:00
Brian Gaeke
51b16fc65a Make SparcV9RegInfo::getRegType() return the right answer for registers 
of IntCC, FloatCC, and Special types.

Make SparcV9RegInfo::getRegClassIDOfRegType() return the right answer
if you ask for the class corresponding to SpecialRegType.

llvm-svn: 13095
 2004-04-21 17:53:58 +00:00
Brian Gaeke
3727c760ed Make it legal to ask for the type of a specialreg 
llvm-svn: 13078
 2004-04-20 20:12:57 +00:00
Brian Gaeke
047739f8d8 Make it legal to request a load or store of %fsr. 
llvm-svn: 13073
 2004-04-19 19:12:12 +00:00
Brian Gaeke
3dfe9f19ea Regularize include guards and remove some excess whitespace. 
llvm-svn: 13071
 2004-04-19 18:53:44 +00:00
Brian Gaeke
d7fa9142a3 Tighten up SparcV9FloatCCRegClass::getRegName()'s assertion - if you ask it for 
the name of %fsr (as the comment in SparcV9RegClassInfo.h used to suggest)
you would walk off the end of the FloatCCRegName array.

llvm-svn: 13070
 2004-04-19 18:53:43 +00:00
Brian Gaeke
5bcbc23fc1 Regularize include guards, remove some excess whitespace and fix some comments. 
Remove the extra %fsr register from SparcV9FloatCCRegClass.

llvm-svn: 13069
 2004-04-19 18:53:42 +00:00
Brian Gaeke
e708b1d5ef Give SparcV9CodeEmitter a head-of-file comment and a PassName. 
llvm-svn: 12967
 2004-04-15 20:23:13 +00:00
John Criswell
8a4525ae64 Remove code to adjust the iterator for llvm.readio and llvm.writeio. 
The iterator is pointing at the next instruction which should not disappear
when doing the load/store replacement.

llvm-svn: 12954
 2004-04-14 21:27:56 +00:00
Brian Gaeke
8e2fb33172 Fix typo. 
llvm-svn: 12953
 2004-04-14 21:21:56 +00:00
Chris Lattner
64431dbce7 This is the real fix for Codegen/X86/2004-04-13-FPCMOV-Crash.llx which works 
even when the "optimization" I added before is turned off.  It generates this
extremely pointless code:

test:
        fld QWORD PTR [%ESP + 4]
        mov %AL, 0
        test %AL, %AL
        fcmove %ST(0), %ST(0)
        ret

Good thing the optimizer will have removed this before code generation
anyway.  :)

llvm-svn: 12939
 2004-04-14 02:42:32 +00:00
John Criswell
94de925685 Added support for the llvm.readio and llvm.writeio intrinsics. 
On x86, memory operations occur in-order, so these are just lowered into
volatile loads and stores.

llvm-svn: 12936
 2004-04-13 22:13:14 +00:00
Chris Lattner
2ba048528f Implement a small optimization, which papers over the problem in 
X86/2004-04-13-FPCMOV-Crash.llx

A more robust fix is to follow.

llvm-svn: 12935
 2004-04-13 21:56:09 +00:00
Brian Gaeke
336b83623a I don't think we have to have 4 extra allocated (but unused) bytes on the stack. 
llvm-svn: 12905
 2004-04-13 18:28:37 +00:00
Brian Gaeke
6d8a362874 I started working on casts, but I don't have anything compilable yet. 
llvm-svn: 12903
 2004-04-13 18:27:46 +00:00
Chris Lattner
8b6bc380e3 Emit the immediate form of in/out when possible. 
Fix several bugs in the intrinsics:
  1. Make sure to copy the input registers before the instructions that use them
  2. Make sure to copy the value returned by 'in' out of EAX into the register
     it is supposed to be in.

This fixes assertions when using in/out and linear scan.

llvm-svn: 12896
 2004-04-13 17:20:37 +00:00
Chris Lattner
15ac62827e Add immediate forms of in/out. Use let to shorten lines 
llvm-svn: 12895
 2004-04-13 17:19:31 +00:00
Chris Lattner
ecbade26d5 Add support for new instruction type 
llvm-svn: 12894
 2004-04-13 17:18:51 +00:00
Chris Lattner
e8e60bf45f Add support for the printImplicitDefsBefore flag 
llvm-svn: 12893
 2004-04-13 17:18:39 +00:00
Brian Gaeke
36093cb38c We don't need to insert TargetData into the PassManager here. 
llvm-svn: 12874
 2004-04-12 21:46:31 +00:00
Chris Lattner
43f754339a Fix issues that the local allocator has dealing with instructions that implicitly use ST(0) 
llvm-svn: 12855
 2004-04-12 03:02:48 +00:00
Chris Lattner
9cdc472518 No really, fix printing for LLC. I gotta get a way for CVS to whine at me if 
I have unsaved emacs buffers, geeze...

llvm-svn: 12854
 2004-04-12 01:52:04 +00:00
Chris Lattner
f1d59be0e8 Correct printing for LLC and the encoding for the JIT 
llvm-svn: 12853
 2004-04-12 01:50:04 +00:00
Chris Lattner
682a6361c7 Use the fucomi[p] instructions to perform floating point comparisons instead 
of the fucom[p][p] instructions.  This allows us to code generate this function

bool %test(double %X, double %Y) {
        %C = setlt double %Y, %X
        ret bool %C
}

... into:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucomip %ST(1)
        fstp %ST(0)
        setb %AL
        movsx %EAX, %AL
        ret

where before we generated:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucompp
**      fnstsw
**      sahf
        setb %AL
        movsx %EAX, %AL
        ret

The two marked instructions (which are the ones eliminated) are very bad,
because they serialize execution of the processor.  These instructions are
available on the PPRO and later, but since we already use cmov's we aren't
losing any portability.

I retained the old code for the day when we decide we want to support back
to the 386.

llvm-svn: 12852
 2004-04-12 01:43:36 +00:00
Chris Lattner
c85d92e0b7 Add support for the FUCOMIr instruction 
llvm-svn: 12851
 2004-04-12 01:39:15 +00:00
Chris Lattner
cfb7144bf1 Add two new instructions 
llvm-svn: 12850
 2004-04-12 01:38:55 +00:00
Chris Lattner
de47ad3d6f Fix a bug in my load/cast folding patch. 
llvm-svn: 12849
 2004-04-12 00:23:04 +00:00
Chris Lattner
b3a10e244a Adjust some comments, fix a bug in my previous patch 
llvm-svn: 12848
 2004-04-12 00:12:04 +00:00
Chris Lattner
24f8b11206 On X86, casting an integer to floating point requires going through memory. 
If the source of the cast is a load, we can just use the source memory location,
without having to create a temporary stack slot entry.

Before we code generated this:

double %int(int* %P) {
        %V = load int* %P
        %V2 = cast int %V to double
        ret double %V2
}

into:

int:
        sub %ESP, 4
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        mov DWORD PTR [%ESP], %EAX
        fild DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we produce this:

int:
        mov %EAX, DWORD PTR [%ESP + 4]
        fild DWORD PTR [%EAX]
        ret

... which is nicer.

llvm-svn: 12846
 2004-04-11 23:21:26 +00:00
Chris Lattner
95cf3f8765 Implement folding of loads into floating point operations. This implements: 
test/Regression/CodeGen/X86/fp_load_fold.llx

llvm-svn: 12844
 2004-04-11 22:05:45 +00:00
Chris Lattner
b611f10e74 Unify all of the code for floating point +,-,*,/ into one function 
llvm-svn: 12842
 2004-04-11 21:23:56 +00:00
Chris Lattner
3378d71a55 This implements folding of constant operands into floating point operations 
for mul and div.

Instead of generating this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_divr_0]
        fdivrp %ST(1)
        ret

We now generate this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fdivr QWORD PTR [.CPItest_divr_0]
        ret

This code desperately needs refactoring, which will come in the next
patch.

llvm-svn: 12841
 2004-04-11 21:09:14 +00:00
Chris Lattner
833d84f48a Restructure the mul/div/rem handling code to follow the pattern the other 
instructions use.  This doesn't change any functionality except that long
constant expressions of these operations will now magically start working.

llvm-svn: 12840
 2004-04-11 20:56:28 +00:00
Chris Lattner
69304a897c Codegen FP adds and subtracts with a constant more efficiently, generating: 
fld QWORD PTR [%ESP + 4]
        fadd QWORD PTR [.CPItest_add_0]

instead of:

        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_add_0]
        faddp %ST(1)

I also intend to do this for mul & div, but it appears that I have to
refactor a bit of code before I can do so.

This is tested by: test/Regression/CodeGen/X86/fp_constant_op.llx

llvm-svn: 12839
 2004-04-11 20:26:20 +00:00
Chris Lattner
dda382531e Add some new instructions 
llvm-svn: 12838
 2004-04-11 20:24:15 +00:00
Chris Lattner
a0681183b6 Relax assertion to make this function work with a broader class of instructions 
llvm-svn: 12836
 2004-04-11 20:21:06 +00:00
Chris Lattner
d22a1894a0 Two changes: 
1. If an incoming argument is dead, don't load it from the stack
  2. Do not code gen noop copies at all (ie, cast int -> uint), not even to
     a move.  This should reduce register pressure for allocators that are
     unable to coallesce away these copies in some cases.

llvm-svn: 12835
 2004-04-11 19:21:59 +00:00
Chris Lattner
8b1122d4dc Silence a spurious warning 
llvm-svn: 12815
 2004-04-10 18:32:01 +00:00
John Criswell
c9c191c41b Reversed the order of the llvm.writeport() operands so that the value 
is listed first and the address is listed second.

llvm-svn: 12795
 2004-04-09 19:09:14 +00:00
John Criswell
a52a2291d8 Changed assertions to error messages. 
llvm-svn: 12787
 2004-04-09 15:10:15 +00:00
John Criswell
8740c3767d Changes recommended by Chris: 
InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786
 2004-04-08 22:39:13 +00:00
John Criswell
f6b16ea70b Added the llvm.readport and llvm.writeport intrinsics for x86. These do 
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782
 2004-04-08 20:31:47 +00:00
Brian Gaeke
bd29266df4 Don't include InstrSelectionSupport.h. 
llvm-svn: 12766
 2004-04-07 20:55:32 +00:00
Brian Gaeke
c48a77d1ba Move ChooseRegOrImmed() prototype here, from InstrSelectionSupport.h. 
llvm-svn: 12765
 2004-04-07 20:38:57 +00:00
Brian Gaeke
54245d895a Don't include InstrSelectionSupport.h. 
llvm-svn: 12764
 2004-04-07 20:38:56 +00:00
Brian Gaeke
1193590133 Fix insertion of SelectInsts. 
llvm-svn: 12760
 2004-04-07 18:31:47 +00:00
Brian Gaeke
6badc5d83b Don't print [%reg + 0], just print [%reg] 
llvm-svn: 12759
 2004-04-07 17:33:56 +00:00
Brian Gaeke
cb5141b4de First version of code to handle loads. Stub function for handling stores. 
llvm-svn: 12758
 2004-04-07 17:29:37 +00:00
Brian Gaeke
3e29bc5a19 Support loading arguments from %I0...%I5 into virtual registers in 
function prologues, and fix an off-by-one in visitCallInst that was
putting call args into the wrong registers.

llvm-svn: 12757
 2004-04-07 17:04:09 +00:00
Brian Gaeke
3eb6c1d3ae It's setting up the call args right now, but on the callee side, it's 
trying to get incoming args off the stack, instead of the %i0...%i6 regs,
which is wrong.

llvm-svn: 12756
 2004-04-07 16:41:22 +00:00
Chris Lattner
37a392dc52 This is a start on handling setcc instructions. As the comment notes, we 
have no good way of handling this until the code generator is improved.
We should probably just emit V9 instructions in the meantime.

llvm-svn: 12745
 2004-04-07 05:04:51 +00:00
Chris Lattner
bb67452b4b andd subcc instructions which is used to create the 'cmp' pseudo instruction 
llvm-svn: 12744
 2004-04-07 05:04:01 +00:00
Chris Lattner
2f63fbf9d5 Avoid emitting an extra copy on each 32-bit operation 
llvm-svn: 12743
 2004-04-07 04:36:53 +00:00
Brian Gaeke
d98edc771e Make generation of stack-slot loads and copies less ugly. 
llvm-svn: 12742
 2004-04-07 04:29:14 +00:00
Brian Gaeke
90c53bcbda Fix bug in printing loads. 
llvm-svn: 12741
 2004-04-07 04:29:03 +00:00
Chris Lattner
be45dbdaf8 Add support for shift instructions, wrap some long lines 
llvm-svn: 12740
 2004-04-07 04:27:16 +00:00
Chris Lattner
ded6e64b53 Fix encoding of existing shift instructions, add rr shifts 
llvm-svn: 12739
 2004-04-07 04:26:57 +00:00
Chris Lattner
13546cb380 Add a bunch more instructions 
llvm-svn: 12737
 2004-04-07 04:06:46 +00:00
Chris Lattner
a58da750eb Merge my changes with brians 
llvm-svn: 12736
 2004-04-07 04:05:49 +00:00
Brian Gaeke
ece16e53c4 Add in some things I forgot, which Chris helpfully reminded me of... 
llvm-svn: 12735
 2004-04-07 04:05:12 +00:00
Brian Gaeke
4b90f62e6d Add support for the "Y" register, used by MUL & DIV. 
llvm-svn: 12734
 2004-04-07 04:01:11 +00:00
Brian Gaeke
8651efab54 Add UDIV, SDIV, and a few variants of WR. 
llvm-svn: 12733
 2004-04-07 04:01:00 +00:00
Brian Gaeke
0d35bd3ca9 Preliminary support for getting 64-bit integer constants into registers. 
Preliminary support for division. It's gross because you have to initialize
the "Y" register, which is the top 32 bits of the thing you're dividing.

llvm-svn: 12732
 2004-04-07 04:00:49 +00:00
Brian Gaeke
2aa3485241 Prune unnecessary #includes 
llvm-svn: 12731
 2004-04-06 23:25:07 +00:00
Brian Gaeke
c59ef116a2 Simple delay slot filler pass. 
llvm-svn: 12730
 2004-04-06 23:21:45 +00:00
Brian Gaeke
38ad8d1aea Add references to delay slot filler pass. 
Fill in addPassesToJITCompile method.

llvm-svn: 12729
 2004-04-06 23:21:24 +00:00
Brian Gaeke
0ee6eb1c1a First attempt at handling frame index elimination. 
llvm-svn: 12728
 2004-04-06 22:10:22 +00:00
Brian Gaeke
b7f86edbf3 First attempt at special-casing printing of [%reg + offset] for 
ld/st instructions - doesn't seem to work yet, but I think it's
just a typo or something somewhere.

llvm-svn: 12727
 2004-04-06 22:10:11 +00:00
Brian Gaeke
74d26802a4 Delete reference to "the Mach-O Runtime ABI". 
llvm-svn: 12726
 2004-04-06 22:09:59 +00:00
Brian Gaeke
da22005285 Deal with call return values. 
Don't put NOPs in delay slots at all. We'll have a fix-up pass later.

llvm-svn: 12725
 2004-04-06 22:09:23 +00:00
Jakub Staszak
fc0d9bb7e9 file based off InstSelectSimple.cpp, slowly being replaced by generated code from the really simple X86 instruction selector tablegen backend 
llvm-svn: 12715
 2004-04-06 19:35:17 +00:00
Jakub Staszak
06dc0add14 Tablgen files for really simple instruction selector 
llvm-svn: 12714
 2004-04-06 19:34:00 +00:00
Chris Lattner
3808778190 Fix PR313: [x86] JIT miscompiles unsigned short to floating point 
llvm-svn: 12711
 2004-04-06 19:29:36 +00:00
Chris Lattner
993d6106c7 Fix incorrect encoding of some ADC and SBB instuctions 
llvm-svn: 12710
 2004-04-06 19:20:32 +00:00
Chris Lattner
54e93df11a Fix a minor bug in previous checking 
Enable folding of long seteq/setne comparisons into branches and select instructions
Implement unfolded long relational comparisons against a constants a bit more efficiently

Folding comparisons changes code that looks like this:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

into code that looks like this:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        jne .LBB2 # PC rel: F

This speeds up 186.crafty by 6% with llc-ls.

llvm-svn: 12702
 2004-04-06 17:34:50 +00:00
Chris Lattner
2d9b28ac0b Improve codegen of long == and != comparisons against constants. Before, 
comparing a long against zero got us this:

        sub %ESP, 8
        mov DWORD PTR [%ESP + 4], %ESI
        mov DWORD PTR [%ESP], %EDI
        mov %EAX, DWORD PTR [%ESP + 12]
        mov %EDX, DWORD PTR [%ESP + 16]
        mov %ECX, 0
        mov %ESI, 0
        mov %EDI, %EAX
        xor %EDI, %ECX
        mov %ECX, %EDX
        xor %ECX, %ESI
        or %EDI, %ECX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

Now it gets us this:

        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

llvm-svn: 12696
 2004-04-06 16:02:27 +00:00
Chris Lattner
fd7b570dff Handle various other important cases of multiplying a long constant immediate. For 
example, multiplying X*(1 + (1LL << 32)) now produces:

test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %ECX
        add %EDX, %ECX
        ret

[[[Note to Alkis: why isn't linear scan generating this code??  This might be a
 problem with your intervals being too conservative:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        add %EDX, %EAX
        ret

end note]]]

Whereas GCC produces this:

T:
        sub     %esp, 12
        mov     %edx, DWORD PTR [%esp+16]
        mov     DWORD PTR [%esp+8], %edi
        mov     %ecx, DWORD PTR [%esp+20]
        xor     %edi, %edi
        mov     DWORD PTR [%esp], %ebx
        mov     %ebx, %edi
        mov     %eax, %edx
        mov     DWORD PTR [%esp+4], %esi
        add     %ebx, %edx
        mov     %edi, DWORD PTR [%esp+8]
        lea     %edx, [%ecx+%ebx]
        mov     %esi, DWORD PTR [%esp+4]
        mov     %ebx, DWORD PTR [%esp]
        add     %esp, 12
        ret

I'm not sure example what GCC is smoking here, but it looks like it has just
confused itself with a bunch of stack slots or something.  The intel compiler
is better, but still not good:

T:
        movl      4(%esp), %edx                                 #2.11
        movl      8(%esp), %eax                                 #2.11
        lea       (%eax,%edx), %ecx                             #3.12
        movl      $1, %eax                                      #3.12
        mull      %edx                                          #3.12
        addl      %ecx, %edx                                    #3.12
        ret                                                     #3.12

llvm-svn: 12693
 2004-04-06 04:55:43 +00:00
Chris Lattner
6038e5a4a1 Efficiently handle a long multiplication by a constant. For this testcase: 
long %test(long %X) {
        %Y = mul long %X, 123
        ret long %Y
}

we used to generate:

test:
        sub %ESP, 12
        mov DWORD PTR [%ESP + 8], %ESI
        mov DWORD PTR [%ESP + 4], %EDI
        mov DWORD PTR [%ESP], %EBX
        mov %ECX, DWORD PTR [%ESP + 16]
        mov %ESI, DWORD PTR [%ESP + 20]
        mov %EDI, 123
        mov %EBX, 0
        mov %EAX, %ECX
        mul %EDI
        imul %ESI, %EDI
        add %ESI, %EDX
        imul %ECX, %EBX
        add %ESI, %ECX
        mov %EDX, %ESI
        mov %EBX, DWORD PTR [%ESP]
        mov %EDI, DWORD PTR [%ESP + 4]
        mov %ESI, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret

Now we emit:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, 123
        mul %EDX
        imul %ECX, %ECX, 123
        add %ECX, %EDX
        mov %EDX, %ECX
        ret

Which, incidently, is substantially nicer than what GCC manages:
T:
        sub     %esp, 8
        mov     %eax, 123
        mov     DWORD PTR [%esp], %ebx
        mov     %ebx, DWORD PTR [%esp+16]
        mov     DWORD PTR [%esp+4], %esi
        mov     %esi, DWORD PTR [%esp+12]
        imul    %ecx, %ebx, 123
        mov     %ebx, DWORD PTR [%esp]
        mul     %esi
        mov     %esi, DWORD PTR [%esp+4]
        add     %esp, 8
        lea     %edx, [%ecx+%edx]
        ret

llvm-svn: 12692
 2004-04-06 04:29:36 +00:00
Chris Lattner
dd0d31ca2a Improve code generation of long shifts by 32. 
On this testcase:

long %test(long %X) {
        %Y = shr long %X, ubyte 32
        ret long %Y
}

instead of:
t:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        sar %EAX, 0
        mov %EDX, 0
        ret


we now emit:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EDX, 0
        ret

llvm-svn: 12688
 2004-04-06 03:42:38 +00:00
Chris Lattner
7eb61104dc Bugfixes: inc/dec don't set the carry flag! 
llvm-svn: 12687
 2004-04-06 03:36:57 +00:00
Chris Lattner
8cdbb1fe84 Improve code for passing constant longs as arguments to function calls. 
For example, on this instruction:

        call void %test(long 1234)

Instead of this:
        mov %EAX, 1234
        mov %ECX, 0
        mov DWORD PTR [%ESP], %EAX
        mov DWORD PTR [%ESP + 4], %ECX
        call test

We now emit this:
        mov DWORD PTR [%ESP], 1234
        mov DWORD PTR [%ESP + 4], 0
        call test

llvm-svn: 12686
 2004-04-06 03:23:00 +00:00
Chris Lattner
2738d6d4a4 Emit more efficient 64-bit operations when the RHS is a constant, and one 
of the words of the constant is zeros.  For example:
  Y = and long X, 1234

now generates:
  Yl = and Xl, 1234
  Yh = 0

instead of:
  Yl = and Xl, 1234
  Yh = and Xh, 0

llvm-svn: 12685
 2004-04-06 03:15:53 +00:00
Chris Lattner
bdbedf9523 Fix typeo 
llvm-svn: 12684
 2004-04-06 02:13:25 +00:00
Chris Lattner
606639ed1a Add support for simple immediate handling to long instruction selection. 
This allows us to handle code like 'add long %X, 123456789012' more efficiently.

llvm-svn: 12683
 2004-04-06 02:11:49 +00:00
Chris Lattner
e84f12a165 The sbb instructions really ARE sbb's, not adc's 
llvm-svn: 12682
 2004-04-06 02:02:11 +00:00
Chris Lattner
0808f5daa5 Implement negation of longs efficiently. For this testcase: 
long %test(long %X) {
        %Y = sub long 0, %X
        ret long %Y
}

We used to generate:

test:
        sub %ESP, 4
        mov DWORD PTR [%ESP], %ESI
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %ESI, DWORD PTR [%ESP + 12]
        mov %EAX, 0
        mov %EDX, 0
        sub %EAX, %ECX
        sbb %EDX, %ESI
        mov %ESI, DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we generate:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        neg %EAX
        adc %EDX, 0
        neg %EDX
        ret

llvm-svn: 12681
 2004-04-06 01:48:06 +00:00
Chris Lattner
56dcdcf638 Minor tweak to avoid an extra reg-reg copy that the register allocator has to eliminate 
llvm-svn: 12680
 2004-04-06 01:25:33 +00:00
Chris Lattner
42cf317fca Two changes: 
* In promote32, if we can just promote a constant value, do so instead of
    promoting a constant dynamically.
  * In visitReturn inst, actually USE the promote32 argument that takes a
    Value*

The end result of this is that we now generate this:

test:
        mov %EAX, 0
        ret

instead of...

test:
        mov %AX, 0
        movzx %EAX, %AX
        ret

for:

ushort %test() {
        ret ushort 0
}

llvm-svn: 12679
 2004-04-06 01:21:00 +00:00
Chris Lattner
9236135e8f Support getelementptr instructions which use uint's to index into structure 
types and can have arbitrary 32- and 64-bit integer types indexing into
sequential types.

llvm-svn: 12653
 2004-04-05 01:30:19 +00:00
Chris Lattner
c69fd63e82 In the perhaps not-to-distant future, we might support gep instructions that 
have non-long indices for sequential types.  In order to avoid trying to figure
out how the v9 backend works, we'll just hack it in the preselection pass.

llvm-svn: 12647
 2004-04-04 20:44:05 +00:00
Brian Gaeke
dec12ea71d Add support for many of the MRegisterInfo callbacks. 
Eliminating call-frame pseudo instrs and frame indices are still stubs.
Flesh out the emitPrologue method based on better ABI knowledge.

llvm-svn: 12632
 2004-04-02 20:53:37 +00:00
Brian Gaeke
b2d36cced3 Add load, store, and NOP instructions. 
Fix up comments.

llvm-svn: 12631
 2004-04-02 20:53:37 +00:00
Brian Gaeke
741518f9f6 Add support for printing pc-relative displacements of functions (as used in 
the CALL instruction).

llvm-svn: 12630
 2004-04-02 20:53:35 +00:00
Brian Gaeke
10ab592570 Add support for call instructions (0-ary only for now). 
llvm-svn: 12629
 2004-04-02 20:53:33 +00:00
Alkis Evlogimenos
27ed33c309 Clean up code a bit. 
llvm-svn: 12615
 2004-04-02 18:11:32 +00:00
Brian Gaeke
73afcebba1 Only strip symbols if emitting bytecode to the assembly file. 
Move lowerselect pass to come after preselection.  Move machine
code construction and stack slots pass to come right before instruction
selection. This is to help fix perlbmk.

Update comments.

Make the sequence of passes in addPassesToJITCompile look more like
the sequence of passes in addPassesToEmitAssembly, including support
for -print-machineinstrs.

llvm-svn: 12614
 2004-04-02 17:52:40 +00:00
Brian Gaeke
3fb4f87195 Add support for constant select expressions. Clarify the assertion failure msg. 
llvm-svn: 12613
 2004-04-02 17:52:29 +00:00
Alkis Evlogimenos
85e007a6dc Fix type in comments 
llvm-svn: 12611
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
84ee10f9e1 Fix type in instruction builder instantiation 
llvm-svn: 12610
 2004-04-02 15:51:03 +00:00
Alkis Evlogimenos
20b074682c Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner
ef90bac3e3 Add support for select constant expressions to the CBE, fixing SIOD 
llvm-svn: 12589
 2004-04-01 05:28:26 +00:00
Chris Lattner
b6e4e5a95e Simplify code by using the more powerful BuildMI forms. 
Implement a small optimization.  In test/Regression/CodeGen/X86/select.ll,
we now generate this for foldSel3:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fstp %ST(1)
        ret

Instead of:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fxch %ST(1)
***     fstp %ST(0)
        ret

In practice, this only effects code size: performance should be basically
unaffected.

llvm-svn: 12588
 2004-04-01 04:06:09 +00:00
Chris Lattner
78027ca4ff Wrap at 80 cols 
llvm-svn: 12587
 2004-04-01 04:03:27 +00:00
Chris Lattner
2e0755a058 Generate slightly smaller code, "test R, R" instead of "cmp R, 0" 
llvm-svn: 12579
 2004-03-31 22:22:36 +00:00
Chris Lattner
97e8b80649 The X86 backend no longer needs the select lowering pass. 
llvm-svn: 12578
 2004-03-31 22:03:46 +00:00
Chris Lattner
e5d60adc20 Codegen FP select instructions into X86 conditional moves. Annoyingly enough 
the X86 does not support a full set of fp cmove instructions, so we can't always
fold the condition into the select.  :(  Yuck.

llvm-svn: 12577
 2004-03-31 22:03:35 +00:00