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1694 Commits

Author SHA1 Message Date
Misha Brukman
a2ac4e4345 Use the common `NoFPElim' setting instead of our own. 
llvm-svn: 14298
 2004-06-21 21:10:24 +00:00
Misha Brukman
2f580c043c Implement `NoFPElim' in a target-agnostic fashion so it can be shared. 
llvm-svn: 14297
 2004-06-21 21:08:45 +00:00
Misha Brukman
a79674d478 * Make indentation consistent at 2 chars 
* Doxygenify function comments
* Wrap code at 80 cols

llvm-svn: 14295
 2004-06-21 20:22:03 +00:00
Misha Brukman
4424ef9dd1 This file is no longer applicable. 
llvm-svn: 14294
 2004-06-21 20:17:41 +00:00
Misha Brukman
3d93b9ccca llvm/IntrinsicLowering.h => llvm/CodeGen/IntrinsicLowering.h 
llvm-svn: 14292
 2004-06-21 18:30:31 +00:00
Misha Brukman
36089f7034 Intrinsic::isnan has gone away, support for it commented out. 
Intrinsic::isunordered has arrived, and we just use the standard lowering
pass for it.

llvm-svn: 14290
 2004-06-21 17:58:36 +00:00
Misha Brukman
1c26b2e29d Convert tabs to spaces. 
llvm-svn: 14289
 2004-06-21 17:41:12 +00:00
Misha Brukman
30e1885192 Type::getPrimitiveID() -> getTypeID() 
llvm-svn: 14288
 2004-06-21 17:25:55 +00:00
Misha Brukman
76b4796e7c Type::getPrimitiveID() -> getTypeID() 
llvm-svn: 14287
 2004-06-21 17:19:08 +00:00
Misha Brukman
269034c151 Initial revision 
llvm-svn: 14283
 2004-06-21 16:55:25 +00:00
Chris Lattner
cc465361d9 Move the IntrinsicLowering header into the CodeGen directory, as per PR346 
llvm-svn: 14266
 2004-06-20 07:49:54 +00:00
Brian Gaeke
26336244f5 .zero doesn't work in the Solaris assembler. 
llvm-svn: 14231
 2004-06-18 08:59:16 +00:00
Brian Gaeke
6a8de685b3 Get rid of selects the easy way 
llvm-svn: 14230
 2004-06-18 08:46:15 +00:00
Brian Gaeke
a9daa0a519 Make visitAllocaInst() look more like its X86 counterpart. 
llvm-svn: 14229
 2004-06-18 08:45:52 +00:00
Brian Gaeke
ab4687b176 Mess around with allocation order. In particular, I think we ought to be 
using the local & in regs first because they are not clobbered by calls.

llvm-svn: 14228
 2004-06-18 08:19:08 +00:00
Brian Gaeke
f5697cf56c JMPL has a delay slot. 
llvm-svn: 14227
 2004-06-18 08:18:54 +00:00
Brian Gaeke
2a5dec63a6 Clean up the commented-out F3_3 stuff. 
Replace it with a working class for FP instrs.

llvm-svn: 14226
 2004-06-18 06:28:21 +00:00
Brian Gaeke
01309de73d Fix jmpl. 
Add some FP moves.

llvm-svn: 14225
 2004-06-18 06:28:10 +00:00
Brian Gaeke
c045f38dcb Support printing base+offset pairs where the offset is a register. 
Use this for printing the jmpl indirect-call instruction.

llvm-svn: 14224
 2004-06-18 06:27:59 +00:00
Brian Gaeke
92a3e14ac4 Support intrinsic calls (although no particular intrinsics are supported yet). 
Support indirect calls.
Support returning a float value.

llvm-svn: 14223
 2004-06-18 06:27:48 +00:00
Brian Gaeke
c5f1146e62 Add load instructions for floating-point registers. 
llvm-svn: 14217
 2004-06-18 05:19:27 +00:00
Brian Gaeke
7a618842f1 Support alloca instructions. 
Support copying floating-point constants to registers.
Add assertion to visitCallInst to abort if we hit a NULL calledFunction, for now.

llvm-svn: 14216
 2004-06-18 05:19:16 +00:00
Chris Lattner
9e1bbe86ba Codegen sub C, X a little bit better for register pressure. Instead of 
mov REG, C
sub REG, X

generate:

neg X
add X, C

which uses one less reg

llvm-svn: 14213
 2004-06-18 00:50:37 +00:00
Chris Lattner
a5750b975a Fold setcc instructions into select and branches that are not in the same BB as 
the setcc.

llvm-svn: 14212
 2004-06-18 00:29:22 +00:00
Brian Gaeke
b824469b44 Make storeRegToStackSlot slightly shorter. 
Make copyRegToReg return 1 instead of -1.
Edit a comment in emitPrologue().

llvm-svn: 14211
 2004-06-17 22:34:48 +00:00
Brian Gaeke
9a0dc64af6 Set the isBranch and isTerminator flags on branch instructions correctly. 
Add a FIXME about the (currently unused) JMPL instructions.

llvm-svn: 14210
 2004-06-17 22:34:29 +00:00
Brian Gaeke
c82f209e72 Emit stores correctly; don't fail an assertion. 
llvm-svn: 14209
 2004-06-17 22:34:19 +00:00
Brian Gaeke
d084a534a2 Support generating machine instructions for Phi nodes (based on x86, but with 
modifications for 1 LLVM BB --> many MBBs).
Fix store operand order: make it always be Base, Offset, SrcReg (think
"[ Base + Offset ] = SrcReg").
Rewrite visitBranchInst() to be even dumber (but working) -- give up on
the branch fallthrough trick, for the time being.
Make visitSetCondInst() work.

llvm-svn: 14208
 2004-06-17 22:34:08 +00:00
Brian Gaeke
af2408a4ee Recognize more branches. 
llvm-svn: 14207
 2004-06-17 22:33:57 +00:00
Chris Lattner
f815117481 Do not fold loads into instructions if it is used more than once. In particular 
we do not want to fold the load in cases like this:

  X = load
    = add A, X
    = add B, X

llvm-svn: 14204
 2004-06-17 22:15:25 +00:00
Brian Gaeke
7d711d517b Use addGlobalAddress and addMBB for call & branch targets instead of addPCDisp. 
Abort if we see a PCRelativeDisp MachineOperand, to be safe. This matches
the X86 backend.

llvm-svn: 14202
 2004-06-17 19:39:23 +00:00
Chris Lattner
0cd29ae2cd Rename Type::PrimitiveID to TypeId and ::getPrimitiveID() to ::getTypeID() 
llvm-svn: 14201
 2004-06-17 18:19:28 +00:00
Chris Lattner
9bb0083d16 Remove support for llvm.isnan. Alkis wins :) 
llvm-svn: 14189
 2004-06-15 21:48:07 +00:00
Chris Lattner
d11493d8c4 Add basic support for the isunordered intrinsic. The isnan stuff still needs to go 
llvm-svn: 14185
 2004-06-15 21:36:44 +00:00
Brian Gaeke
0a7b268b1a Fix thinko in visitor... ShiftInsts should currently be delegated 
to visitBinaryOperator.

llvm-svn: 14182
 2004-06-15 21:09:46 +00:00
Brian Gaeke
5fe5e06bea I think we'll use the standard lowering passes for now. 
llvm-svn: 14179
 2004-06-15 20:37:12 +00:00
Brian Gaeke
d5f45ba4a1 Fix bug generating code for void call instructions: don't call 
getReg() on void value.

llvm-svn: 14178
 2004-06-15 20:06:32 +00:00
Brian Gaeke
79008f4648 Squash a warning from the Solaris assembler by aligning the stack 
on a double-word boundary instead of a single-word boundary.

llvm-svn: 14177
 2004-06-15 19:53:10 +00:00
Brian Gaeke
e02c780919 Allow special-casing of operand printing based on opcode. Print 
non-register, non-immed. arguments to SETHI and OR using %hi() and
%lo() respectively.

llvm-svn: 14176
 2004-06-15 19:52:59 +00:00
Brian Gaeke
b158cb6411 Support constant GEP expressions. 
Support copying long constants to register pairs.
Support copying ConstantPointerNulls and ConstantPointerRefs to registers.

llvm-svn: 14175
 2004-06-15 19:16:07 +00:00
Misha Brukman
130e02f232 Add file comment. 
llvm-svn: 14172
 2004-06-14 15:13:59 +00:00
Brian Gaeke
21e2dd53d8 Make -print-machineinstrs even stronger. You get to see the final code after 
peepholing, and make it work the same way in the JIT as in LLC.

llvm-svn: 14170
 2004-06-14 05:05:45 +00:00
Chris Lattner
3a8e675c03 By far, one of the most common uses of isnan is to make 'isunordered' 
comparisons.  In an 'isunordered' predicate, which looks like this at
the LLVM level:

        %a = call bool %llvm.isnan(double %X)
        %b = call bool %llvm.isnan(double %Y)
        %COM = or bool %a, %b

We used to generate this code:

        fxch %ST(1)
        fucomip %ST(0), %ST(0)
        setp %AL
        fucomip %ST(0), %ST(0)
        setp %AH
        or %AL, %AH

With this patch, we generate this code:

        fucomip %ST(0), %ST(1)
        fstp %ST(0)
        setp %AL

Which should make alkis happy.  Tested as X86/compare_folding.llx:test1

llvm-svn: 14148
 2004-06-11 05:33:49 +00:00
Chris Lattner
f78e3e7f63 Fix bug in previous checkin 
llvm-svn: 14146
 2004-06-11 05:22:44 +00:00
Chris Lattner
7d8093efb1 No really, these are dead now 
llvm-svn: 14145
 2004-06-11 04:50:14 +00:00
Chris Lattner
a8e603b719 Now that compare instructions aren't lumped in with the other twoargfp instructions, 
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144
 2004-06-11 04:49:02 +00:00
Chris Lattner
b050f778ca Introduce a new FP instruction type to separate the compare cases from the 
twoarg cases.

llvm-svn: 14143
 2004-06-11 04:41:24 +00:00
Chris Lattner
edb06042b9 Add direct support for the isnan intrinsic, implementing test/Regression/CodeGen/X86/isnan.llx 
testcase

llvm-svn: 14141
 2004-06-11 04:31:10 +00:00
Chris Lattner
4c8b57ea31 Add support for the setp instructions 
llvm-svn: 14140
 2004-06-11 04:30:06 +00:00
Chris Lattner
c66e996765 Split compare instruction handling OUT of handleTwoArgFP into handleCompareFP. 
This makes the code much simpler, and the two cases really do belong apart.
Once we do it, it's pretty obvious how flawed the logic was for A != A case,
so I fixed it (fixing PR369).

This also uses freeStackSlotAfter instead of inserting an fxchg then
popStackAfter'ing in the case where there is a dead result (unlikely, but
possible), producing better code.

llvm-svn: 14139
 2004-06-11 04:25:06 +00:00