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24998 Commits

Author SHA1 Message Date
Duncan Sands
8d5640ac90 Fix PR2792: treat volatile loads as writing memory somewhere. 
Treat stores as reading memory, just to play safe.

llvm-svn: 56188
 2008-09-13 12:45:50 +00:00
Evan Cheng
63b98ccd5e Fix random abort. 
llvm-svn: 56184
 2008-09-13 01:55:59 +00:00
Dan Gohman
3450a8252f Define CallSDNode, an SDNode subclass for use with ISD::CALL. 
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183
 2008-09-13 01:54:27 +00:00
Evan Cheng
775a37e4b4 Typo. 
llvm-svn: 56182
 2008-09-13 01:44:01 +00:00
Evan Cheng
200cdea934 Rely on instruction format to determine so_reg operand for now. 
llvm-svn: 56181
 2008-09-13 01:38:29 +00:00
Evan Cheng
0a3a595612 Revert 56176. All those instruction formats are still needed. 
llvm-svn: 56180
 2008-09-13 01:35:33 +00:00
Evan Cheng
1ac0a5f278 Accidentially flipped the condition. 
llvm-svn: 56179
 2008-09-13 01:29:57 +00:00
Evan Cheng
d68f2947a9 Add debug dumps. 
llvm-svn: 56178
 2008-09-13 01:15:21 +00:00
Evan Cheng
18fd8337b3 Eliminate unnecessary instruction formats. 
llvm-svn: 56176
 2008-09-12 23:15:39 +00:00
Evan Cheng
66e7651a16 Addrmode 1 S bit can be dynamically set. Look for CPSR def. 
llvm-svn: 56172
 2008-09-12 22:45:55 +00:00
Evan Cheng
adf6720626 Rewrite address mode 1 code emission routines. 
llvm-svn: 56171
 2008-09-12 22:01:15 +00:00
Evan Cheng
07046dae41 On some targets, non-move instructions can become move instructions because of coalescing. e.g. 
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165
 2008-09-12 18:13:14 +00:00
Dan Gohman
082879cfde Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and 
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162
 2008-09-12 18:08:03 +00:00
Dale Johannesen
6395da3510 Pass "earlyclobber" bit through to machine 
representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161
 2008-09-12 17:49:03 +00:00
Dan Gohman
89660301e3 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
 2008-09-12 16:56:44 +00:00
Duncan Sands
94a4573005 Rather than marking all internal globals "Ref" 
when a readonly declaration is called, set a
flag.  This is faster and uses less memory.
In theory it is less accurate, because before
only those internal globals that were read
by someone were being marked "Ref", but now
all are.  But in practice, thanks to other
passes, all internal globals of the kind
considered here will be both read and stored
to: those only read will have been turned
into constants, and those only stored to will
have been deleted.

llvm-svn: 56143
 2008-09-12 07:29:58 +00:00
Dale Johannesen
fbc17046ff The sequence for ppcf128 compares was not IEEE 
safe in the presence of NaNs.

llvm-svn: 56136
 2008-09-12 00:30:56 +00:00
Dan Gohman
0b6d3a9a9b On 64-bit targets, change 32-bit getelementptr indices to be 64-bit 
getelementptr indices, inserting an explicit cast if necessary.
This helps expose the sign-extension operation to other optimizations.

llvm-svn: 56133
 2008-09-11 23:06:38 +00:00
Dan Gohman
5e154a591d Fix a vectorshuffle instcombine bug introduced by r55995. 
Patch by Nicolas Capens!

llvm-svn: 56129
 2008-09-11 22:47:57 +00:00
Jim Grosbach
a25a322741 udpate header comment: s/VP/VFP/ 
llvm-svn: 56126
 2008-09-11 21:41:29 +00:00
Arnold Schwaighofer
adfb111f10 When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case. 
llvm-svn: 56119
 2008-09-11 20:28:43 +00:00
Evan Cheng
5c7e3783ef Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. 
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118
 2008-09-11 20:07:10 +00:00
Owen Anderson
743d45821a Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast isel. 
llvm-svn: 56117
 2008-09-11 19:44:55 +00:00
Duncan Sands
0a66a0ae55 Fix comment typo. 
llvm-svn: 56116
 2008-09-11 19:41:10 +00:00
Duncan Sands
39a7ae3d01 Intrinsics don't touch internal global variables 
(unless passed one via a parameter), even if they
are IntrWriteMem.

llvm-svn: 56115
 2008-09-11 19:35:55 +00:00
Dan Gohman
4ae5fa57b4 Fix a copy+paste bug that Duncan spotted. For several 
cases it was still getting lucky and detecting overflow
but it was clearly incorrect.

llvm-svn: 56113
 2008-09-11 18:53:02 +00:00
Evan Cheng
99be914c9a Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check. 
llvm-svn: 56112
 2008-09-11 18:40:32 +00:00
Duncan Sands
908b7525fa Intrinsics don't read these kinds of global 
variables.

llvm-svn: 56105
 2008-09-11 15:43:12 +00:00
Evan Cheng
9de997d5de Fix a 80 column violation. 
llvm-svn: 56097
 2008-09-11 05:58:06 +00:00
Dale Johannesen
10e1cf3df2 The version of AtomicSDNode::AtomicSDNode used (only) for 
cmp-and-swap reversed the Cmp and Swap arguments; comments
make it clear this is unintentional.  Unfortunately, the
x86 BE had a compensating reversal, which is removed here.
PPC is OK.

From inspection of the Alpha code I think it is OK, but
if somebody has that platform please check it out.  I
cannot test on that platform.

llvm-svn: 56091
 2008-09-11 03:12:59 +00:00
Owen Anderson
139baa5f74 If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up. This fixes 445.gobmk on 
X86-64 in fast isel.

llvm-svn: 56088
 2008-09-11 02:41:37 +00:00
Dale Johannesen
8ac17c1f77 Succumb utterly to compatibility and implement 
__sync_fetch_and_nand as ANDC, even though that's
not what nand means.

llvm-svn: 56087
 2008-09-11 02:15:03 +00:00
Evan Cheng
b879f93ba5 Propagate subreg index when promoting a load to a copy. 
llvm-svn: 56085
 2008-09-11 01:02:12 +00:00
Dan Gohman
36e01356ec In my analysis for r56076 I missed the case where the original 
multiplication overflows.

llvm-svn: 56082
 2008-09-11 00:25:00 +00:00
Dan Gohman
ebfb483309 Fix an icmp+sdiv optimization to check for and handle an overflow 
condition. This fixes PR2740.

llvm-svn: 56076
 2008-09-10 23:30:57 +00:00
Dan Gohman
9eca554828 X86FastISel support for double->float and float->double casts. 
llvm-svn: 56070
 2008-09-10 21:02:08 +00:00
Dan Gohman
ad5824104b FastISel support for i1 PHI nodes. 
llvm-svn: 56069
 2008-09-10 21:01:31 +00:00
Dan Gohman
5a6134a875 FastISel support for i1 constants. 
llvm-svn: 56068
 2008-09-10 21:01:08 +00:00
Owen Anderson
6bcc01b3eb Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it. This 
was exposed by fast isel's handling of shifts on X86-64.  With this, FreeBench/pcompress2 passes on X86-64 in fast isel.

llvm-svn: 56067
 2008-09-10 20:41:13 +00:00
Dan Gohman
3ccdde5eef Add X86FastISel support for static allocas, and refences 
to static allocas. As part of this change, refactor the
address mode code for laods and stores.

llvm-svn: 56066
 2008-09-10 20:11:02 +00:00
Evan Cheng
474ba35954 Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machine operands. 
llvm-svn: 56065
 2008-09-10 20:08:45 +00:00
Evan Cheng
83c694fbe7 Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc. 
llvm-svn: 56061
 2008-09-10 18:25:29 +00:00
Dale Johannesen
3e4bbf01d0 Handle new intrinsics with vector arguments. 
Patch by Paul Redmond.

llvm-svn: 56059
 2008-09-10 17:31:40 +00:00
Dan Gohman
5211f1f5fc Add a break statement that I accidentally deleted when 
I shuffled the fast-isel command-line options around. This fixes
a bunch of fast-isel failures.

llvm-svn: 56057
 2008-09-10 15:52:34 +00:00
Devang Patel
092285d4e4 fix white spaces. 
llvm-svn: 56056
 2008-09-10 14:49:55 +00:00
Duncan Sands
6e9362aeaa Fix name. 
llvm-svn: 56055
 2008-09-10 13:22:10 +00:00
Duncan Sands
c3de6e13df Add trampoline support for the new FastCC calling 
convention (not related to recent Ada testsuite
failures).

llvm-svn: 56054
 2008-09-10 13:11:09 +00:00
Duncan Sands
63ef24bfb1 Turn off the new FastCC for the moment. It causes 
a slew of Ada testsuite failures on x86-32 linux.
Seems to be related to the use of float.

llvm-svn: 56053
 2008-09-10 13:09:24 +00:00
Bill Wendling
c7c5d73866 Remove unnecessary bit-wise AND from the limited precision work. 
llvm-svn: 56049
 2008-09-10 06:26:10 +00:00
Daniel Dunbar
df44fb835c Fix 80 col violation. 
llvm-svn: 56048
 2008-09-10 04:16:29 +00:00