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1086 Commits

Author SHA1 Message Date
Chad Rosier
74c4e2c2d9 Add support for sign-extending non-legal types in SelectSIToFP(). 
llvm-svn: 143603
 2011-11-03 02:04:59 +00:00
Lang Hames
ceec8ec67e Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. 
llvm-svn: 143582
 2011-11-02 22:52:45 +00:00
Chad Rosier
8a613c5ec5 Add support for comparing integer non-legal types. 
llvm-svn: 143559
 2011-11-02 18:08:25 +00:00
Nick Lewycky
5758d6af22 Always use the string pool, even when it makes the .o larger. This may help 
tools that read the debug info in the .o files by making the DIE sizes more
consistent.

llvm-svn: 143186
 2011-10-28 05:29:47 +00:00
Jakob Stoklund Olesen
de21509dcd Also set addrmode6 alignment when align==size. 
Previously, we were only setting the alignment bits on over-aligned
loads and stores.

llvm-svn: 143160
 2011-10-27 22:39:16 +00:00
Evan Cheng
75271d09f1 Avoid partial CPSR dependency from loop backedges. rdar://10357570 
llvm-svn: 143145
 2011-10-27 21:21:05 +00:00
Nick Lewycky
651475977d Teach our Dwarf emission to use the string pool. 
llvm-svn: 143097
 2011-10-27 06:44:11 +00:00
Chad Rosier
e76ba1b654 A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00
Lang Hames
d87e366c7f Make sure short memsets on ARM lower to stores, even when optimizing for size. 
llvm-svn: 143055
 2011-10-26 20:56:52 +00:00
Jim Grosbach
5a61a956cb Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. 
llvm-svn: 143034
 2011-10-26 17:28:15 +00:00
James Molloy
9afc8b08f7 Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance. 
llvm-svn: 143023
 2011-10-26 08:53:19 +00:00
Evan Cheng
941d5c148f Revert part of r142530. The patch potentially hurts performance especially 
on Darwin platforms where -Os means optimize for size without hurting
performance.

llvm-svn: 143002
 2011-10-26 01:17:44 +00:00
Eli Friedman
652497e03c Don't crash on variable insertelement on ARM. PR10258. 
llvm-svn: 142871
 2011-10-24 23:08:52 +00:00
Bill Wendling
e37d737f13 Check the visibility of the global variable before placing it into the stubs 
table. A hidden variable could potentially end up in both lists.
<rdar://problem/10336715>

llvm-svn: 142869
 2011-10-24 23:05:43 +00:00
Chad Rosier
38661ab3ce Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
llvm-svn: 142557
 2011-10-20 00:07:12 +00:00
James Molloy
73a2a8a45e Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
 2011-10-19 14:11:07 +00:00
Bob Wilson
f78f688c02 Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

llvm-svn: 142371
 2011-10-18 17:34:51 +00:00
Bob Wilson
0273c767c8 Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS. 
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization.  For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.

llvm-svn: 142370
 2011-10-18 17:34:47 +00:00
Chad Rosier
eb469f466b Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916

llvm-svn: 142337
 2011-10-18 05:28:00 +00:00
Nadav Rotem
b03ef2cd0b Add CHECKs and document PR11158. 
llvm-svn: 142240
 2011-10-17 20:23:23 +00:00
Nadav Rotem
8ed6f090ef Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00
Eli Friedman
c8d798d91e Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. 
llvm-svn: 142022
 2011-10-14 23:58:49 +00:00
Jakob Stoklund Olesen
2611cc2520 Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746
 2011-10-12 00:06:23 +00:00
Eric Christopher
57c57a3260 Add a new wrapper node for a DILexicalBlock that encapsulates it and a 
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.

This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.

Part of rdar://10246360

llvm-svn: 141729
 2011-10-11 22:59:11 +00:00
Devang Patel
3811b42be0 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689
 2011-10-11 18:09:58 +00:00
Bill Wendling
2606813218 Test simplification that Ana Pazos noticed. 
llvm-svn: 141644
 2011-10-11 04:43:15 +00:00
Bill Wendling
cb617ae8e0 Add testcase for PR11107. 
llvm-svn: 141607
 2011-10-11 00:26:57 +00:00
Devang Patel
e6091c61c7 Revert r141569 and r141576. 
llvm-svn: 141594
 2011-10-10 23:18:02 +00:00
Bill Wendling
7121342ad5 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Devang Patel
c149f390c6 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
 2011-10-10 19:09:20 +00:00
Bill Wendling
7cba44defc Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
 2011-10-10 18:27:30 +00:00
Bob Wilson
b55a64ae72 Reenable tail calls for iOS 5.0 and later. 
llvm-svn: 141370
 2011-10-07 17:17:49 +00:00
Bob Wilson
d8856e17fe Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
llvm-svn: 141368
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov
0944a4c5cc Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!

llvm-svn: 141365
 2011-10-07 16:15:08 +00:00
Cameron Zwarich
cc5f846d58 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

llvm-svn: 141247
 2011-10-05 23:38:50 +00:00
Dan Gohman
779ae47721 Make this test less sensitive to codegen optimizations. 
llvm-svn: 141195
 2011-10-05 18:13:08 +00:00
Jim Grosbach
44047da675 ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Andrew Trick
e1d5ae73ac LSR: rewrite inner loops only. 
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.

llvm-svn: 140762
 2011-09-29 01:33:38 +00:00
Andrew Trick
75c6a45d08 whitespace 
llvm-svn: 140761
 2011-09-29 01:31:48 +00:00
Evan Cheng
1e53900b70 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296

llvm-svn: 140733
 2011-09-28 23:16:31 +00:00
Eli Friedman
56e68f7271 Convert more tests over to the new atomic instructions. 
llvm-svn: 140559
 2011-09-26 20:27:49 +00:00
David Meyer
a6e588d80c PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
llvm-svn: 140516
 2011-09-26 06:13:20 +00:00
Jakob Stoklund Olesen
ca6877343b Also match negative offsets for addrmode3 and addrmode5. 
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

llvm-svn: 140425
 2011-09-23 22:10:33 +00:00
Dan Gohman
d63418e497 Fix SimplifySelectCC to add newly created nodes to the DAGCombiner 
worklist, as it may be possible to perform further optimization on them.

llvm-svn: 140349
 2011-09-22 23:01:29 +00:00
Evan Cheng
ead45e2ba6 Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
llvm-svn: 140181
 2011-09-20 21:38:18 +00:00
Andrew Trick
53aeb9f663 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
 2011-09-20 03:17:40 +00:00
Eli Friedman
b11676fb4b Some additional tests for Thumb atomic load and store (which I somehow forgot to commit earlier). 
llvm-svn: 140074
 2011-09-19 22:02:33 +00:00
Eli Friedman
f7bb39b592 Some legalization fixes for atomic load and store. 
llvm-svn: 139851
 2011-09-15 21:20:49 +00:00
Eli Friedman
08926ecbfb Fix mistake in test runline. 
llvm-svn: 139505
 2011-09-12 17:32:58 +00:00
Eli Friedman
4bae1c4f70 Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. 
llvm-svn: 139407
 2011-09-09 21:04:06 +00:00