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12184 Commits

Author SHA1 Message Date
Dan Gohman
ad6c6a3d33 Fix MachineLICM to use the correct virtual register class when 
unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622
 2009-10-30 22:18:41 +00:00
Bob Wilson
94d79c1f43 Fix a comment. 
llvm-svn: 85610
 2009-10-30 20:13:25 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Dan Gohman
2767aa065e Initial x86 support for BlockAddresses. 
llvm-svn: 85557
 2009-10-30 01:28:02 +00:00
Jim Grosbach
95e1ff2dba Dial back the realignment a bit. 
llvm-svn: 85546
 2009-10-30 00:08:40 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Jim Grosbach
071b4ec891 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.

llvm-svn: 85476
 2009-10-29 02:41:21 +00:00
Bob Wilson
fc1194919b Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426
 2009-10-28 20:46:46 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Evan Cheng
519b231883 fconsts and fconstd are obviously re-materializable. 
llvm-svn: 85410
 2009-10-28 18:19:56 +00:00
Jim Grosbach
e42dc83a9f Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
llvm-svn: 85406
 2009-10-28 17:33:28 +00:00
Evan Cheng
16ed5ac7ff Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
llvm-svn: 85381
 2009-10-28 06:55:03 +00:00
Evan Cheng
5935e48b96 X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. 
llvm-svn: 85379
 2009-10-28 06:30:34 +00:00
Chris Lattner
f605b2e8f9 Previously, all operands to Constant were themselves constant. 
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.

llvm-svn: 85375
 2009-10-28 05:14:34 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Evan Cheng
4e3bc5efb7 Add a second ValueType argument to isFPImmLegal. 
llvm-svn: 85361
 2009-10-28 01:43:28 +00:00
Dan Gohman
b20fae567f Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides 
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.

llvm-svn: 85357
 2009-10-28 00:55:57 +00:00
Bob Wilson
b709aa6b3c Add an indirect branch pattern for ARM. Testcase will be coming soon. 
llvm-svn: 85355
 2009-10-28 00:37:03 +00:00
Chris Lattner
2bc8002f4c rename indbr -> indirectbr to appease the residents of #llvm. 
llvm-svn: 85351
 2009-10-28 00:19:10 +00:00
Bob Wilson
98c9fb94ab Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346
 2009-10-27 23:49:38 +00:00
Bill Wendling
8f96a88125 Add new note. 
llvm-svn: 85341
 2009-10-27 23:30:07 +00:00
Jim Grosbach
7c0566a5cc Enable virtual register based frame index scavenging by default for ARM & T2. 
llvm-svn: 85335
 2009-10-27 22:52:29 +00:00
Bill Wendling
cb9a2f20d5 Move and clarify note. 
llvm-svn: 85334
 2009-10-27 22:48:31 +00:00
Jim Grosbach
a6946f0f50 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333
 2009-10-27 22:45:39 +00:00
Bill Wendling
2aaf2ae6e1 Note corrected. 
llvm-svn: 85332
 2009-10-27 22:43:24 +00:00
Bill Wendling
3e4dd02a1e Modify note. 
llvm-svn: 85331
 2009-10-27 22:40:45 +00:00
Bill Wendling
3edf1d3854 Add a note. 
llvm-svn: 85329
 2009-10-27 22:34:43 +00:00
Chris Lattner
34c90ce60d cppbackend support for indbr 
llvm-svn: 85312
 2009-10-27 21:24:48 +00:00
Chris Lattner
f21034d6c3 CBE support for indbr. 
llvm-svn: 85311
 2009-10-27 21:21:06 +00:00
Johnny Chen
b746e248cd Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
llvm-svn: 85299
 2009-10-27 20:51:49 +00:00
Johnny Chen
d63b06e0f6 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.

llvm-svn: 85297
 2009-10-27 20:45:15 +00:00
Evan Cheng
151726ad30 Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
llvm-svn: 85281
 2009-10-27 19:56:55 +00:00
Bob Wilson
5ca76e601f Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.

llvm-svn: 85280
 2009-10-27 19:52:03 +00:00
Johnny Chen
528c66b30c Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
 2009-10-27 18:44:24 +00:00
Sanjiv Gupta
c690360ed5 Remove unnecessary gotos to fall-thru successors. 
llvm-svn: 85257
 2009-10-27 17:40:24 +00:00
Johnny Chen
37851c95e8 Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Chris Lattner
5596e0eb77 apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :( 
llvm-svn: 85252
 2009-10-27 17:01:03 +00:00
Rafael Espindola
7eb2a8fb0b Correctly align double arguments in the stack. 
llvm-svn: 85235
 2009-10-27 14:09:44 +00:00
Evan Cheng
032eef9720 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng
f30e5556ba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng
a883c2ebb7 Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85178
 2009-10-26 23:45:59 +00:00
Victor Hernandez
673c036bc7 Remove FreeInst. 
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176
 2009-10-26 23:43:48 +00:00
Bob Wilson
5a870f848e Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
 2009-10-26 22:59:12 +00:00
Bob Wilson
ace97183c7 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.

llvm-svn: 85169
 2009-10-26 22:42:13 +00:00
Bob Wilson
32ee4ee163 Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.

llvm-svn: 85167
 2009-10-26 22:34:44 +00:00
Ted Kremenek
acb9fe806e Update CMake files. 
llvm-svn: 85161
 2009-10-26 22:06:01 +00:00
Anton Korobeynikov
4f40949874 Revert r85134, it breaks mingw build 
llvm-svn: 85138
 2009-10-26 18:40:24 +00:00
Sanjiv Gupta
7ea628e8db Make PIC16 overlay a loadable pass. 
llvm-svn: 85134
 2009-10-26 18:22:59 +00:00
David Goodwin
f6199e95b0 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00