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Author SHA1 Message Date
Bill Wendling
6020896a6e This should have been a C++ testcase. 
llvm-svn: 132504
 2011-06-02 22:26:15 +00:00
Jakob Stoklund Olesen
52c6a75ee3 Just use a SmallVector. 
I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.

This should fix the test failures on darwin 9.

llvm-svn: 132500
 2011-06-02 22:22:43 +00:00
Bill Wendling
854ec415ea Testcase for r132493. 
llvm-svn: 132495
 2011-06-02 22:12:42 +00:00
Bill Wendling
8988d1f21f Update for r132493 change. 
llvm-svn: 132494
 2011-06-02 22:11:49 +00:00
Devang Patel
7b9fc618b2 Remove dead code. 
llvm-svn: 132488
 2011-06-02 21:31:00 +00:00
Devang Patel
6455c3f6ae Update DBG_VALUEs while breaking anti dependencies. 
llvm-svn: 132487
 2011-06-02 21:26:52 +00:00
Tanya Lattner
aa1f6df650 Fix encoding for VEXTdf. 
llvm-svn: 132486
 2011-06-02 21:25:24 +00:00
Eli Friedman
0db9c60959 PR10067: Add missing safety check to call return transformation in MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid. 
llvm-svn: 132485
 2011-06-02 21:24:42 +00:00
Devang Patel
1c30f3ac27 During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. 
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!

llvm-svn: 132483
 2011-06-02 20:07:12 +00:00
Rafael Espindola
2eab5458f6 Add test for PR10068. 
llvm-svn: 132482
 2011-06-02 20:02:48 +00:00
Rafael Espindola
1299f014d4 Revert 132424 to fix PR10068. 
llvm-svn: 132479
 2011-06-02 19:57:47 +00:00
Stuart Hastings
bf1b4a2e2e Andy pointed out a dumb omission in this test case. Thanks Andy! 
llvm-svn: 132477
 2011-06-02 19:26:49 +00:00
Eric Christopher
0c337a44e9 Add a new parse hint for multi-letter constraints in inline asm. 
Testcase will come when we use it.

Part of rdar://9119939

llvm-svn: 132476
 2011-06-02 19:26:37 +00:00
Stuart Hastings
af7e57f485 Jakob pointed out a dumb omission in this test case. Thanks Jakob! 
llvm-svn: 132472
 2011-06-02 18:44:05 +00:00
Jakob Stoklund Olesen
b5392437c8 Use RegisterClassInfo::getOrder in RAFast. 
This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.

llvm-svn: 132471
 2011-06-02 18:35:30 +00:00
Jim Grosbach
8a7731f951 .cfi directive register parsing flexibility. 
Parsing a register name/number for .cfi directives can't assume that a
register name starts with a '%' token. Be more flexible and check for a
register number instead. Still unlikely to be perfect, but it allows us
to parse both plain identifiers as register names and integers as register
numbers, which is what we're wanting to support at this point.

llvm-svn: 132466
 2011-06-02 17:14:04 +00:00
Stuart Hastings
8447f18f85 Omit unnecessary stack copy when x87 input is a load. 
rdar://problem/6373334

llvm-svn: 132458
 2011-06-02 15:57:11 +00:00
Benjamin Kramer
e149500163 Start with a zeroed CSRNum map. 
Found by valgrind.

llvm-svn: 132457
 2011-06-02 12:07:44 +00:00
Jakob Stoklund Olesen
a8db700d44 Initialize members to fix problem found by valgrind. 
llvm-svn: 132456
 2011-06-02 05:43:49 +00:00
Jakob Stoklund Olesen
25716baae0 Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

llvm-svn: 132455
 2011-06-02 05:43:46 +00:00
Stuart Hastings
cf5c3fdc33 Tweak testcase for ARM bot. rdar://problem/5993888 
llvm-svn: 132454
 2011-06-02 05:05:39 +00:00
Rafael Espindola
ee123951a2 Don't hardcode the %reg format in the streamer. 
llvm-svn: 132451
 2011-06-02 02:34:55 +00:00
Jakob Stoklund Olesen
24726cedf4 Add a RegisterClassInfo class that lazily caches information about 
register classes.

It provides information for each register class that cannot be
determined statically, like:

- The number of allocatable registers in a class after filtering out the
  reserved and invalid registers.

- The preferred allocation order with registers that overlap callee-saved
  registers last.

- The last callee-saved register that overlaps a given physical register.

This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible.  The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.

Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.

llvm-svn: 132450
 2011-06-02 02:19:35 +00:00
Akira Hatanaka
1f91013bcb Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
llvm-svn: 132448
 2011-06-02 01:03:14 +00:00
Akira Hatanaka
77501e89a7 Test case for r132444. 
llvm-svn: 132445
 2011-06-02 00:25:53 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Eli Friedman
884a7d08b1 When marking a block as being unanalyzable, use "Clobber" on the terminator instead of the first instruction in the block. This is a bit of a hack; "Clobber" isn't really the right marking in the first place. memdep doesn't really have any way of properly expressing "unanalyzable" at the moment. Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though. 
In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated).

The included testcase tests both this commit and r132434.

Part two of rdar://9429882.  (r132434 was mislabeled.)

llvm-svn: 132442
 2011-06-02 00:08:52 +00:00
Chad Rosier
945a780b4e Typos. 
llvm-svn: 132437
 2011-06-01 23:32:40 +00:00
Eli Friedman
37ed424905 In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 . 
Testcase coming up soon.

llvm-svn: 132434
 2011-06-01 23:16:53 +00:00
Devang Patel
03708bbb55 A DBG_VALUE that truncates a range does not start another dbg value range. 
llvm-svn: 132433
 2011-06-01 23:00:17 +00:00
Devang Patel
1a3058d727 Do not drop constant values when a variable's content is described using .debug_loc entries. 
llvm-svn: 132427
 2011-06-01 22:03:25 +00:00
Stuart Hastings
9a085fb9d8 Recommit 132404 with fixes. rdar://problem/5993888 
llvm-svn: 132424
 2011-06-01 21:33:14 +00:00
Eric Christopher
9fe91039e4 Allow bitcasts between valid types of the same size and vector 
types if the vector type is legal.

Fixes rdar://9306086

llvm-svn: 132420
 2011-06-01 19:55:10 +00:00
Stuart Hastings
4b33767382 Revert 132404 to appease a buildbot. rdar://problem/5993888 
llvm-svn: 132419
 2011-06-01 19:52:20 +00:00
Nadav Rotem
4b8e7afe7d Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use 
the TargetLowering enum.

llvm-svn: 132418
 2011-06-01 19:47:10 +00:00
Andrew Trick
b92801a07e SCEV: missing null check fix for r132360, dragonegg crash. 
llvm-svn: 132416
 2011-06-01 19:14:56 +00:00
Jakob Stoklund Olesen
1e7aea1b5e Revert r132358 "Simplify the eviction policy by making the failsafe explicit." 
This commit caused regressions in i386 flops-[568], matrix, salsa20,
256.bzip2, and enc-md5.

llvm-svn: 132413
 2011-06-01 18:45:02 +00:00
Stuart Hastings
b75a0be551 Fix double FGETSIGN to work on x86_32; followup to 132396. 
rdar://problem/5660695

llvm-svn: 132411
 2011-06-01 18:32:25 +00:00
Eric Christopher
d0a9787775 Add a testcase, enabled only on arm, for llvm-gcc r132366. 
llvm-svn: 132409
 2011-06-01 18:23:56 +00:00
Stuart Hastings
cd336a4ee0 Cleanup test case. rdar://problem/5660695 
llvm-svn: 132408
 2011-06-01 18:23:14 +00:00
Benjamin Kramer
d6d9c33cca Initialize IssueWidth to zero. 
Fixes valgrind errors in the CellSPU backend.

llvm-svn: 132405
 2011-06-01 17:19:08 +00:00
Stuart Hastings
23f5ceda96 Add support for x86 CMPEQSS and friends. These instructions do a 
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404
 2011-06-01 17:17:45 +00:00
Stuart Hastings
904f5d9bd7 Reapply 132348 with fixes. rdar://problem/6501862 
llvm-svn: 132402
 2011-06-01 16:42:47 +00:00
Stuart Hastings
d81819d57b A forthcoming SSE patch will break this test; since the test is also 
valid for x87, re-target to x87.  rdar://problem/5993888

llvm-svn: 132401
 2011-06-01 16:13:09 +00:00
Stuart Hastings
159bfd2d1c Test case for 132396. rdar://problem/5660695 
llvm-svn: 132399
 2011-06-01 15:50:29 +00:00
Jakob Stoklund Olesen
283a7e46b5 Fix PR10059 and future variations by handling all register subclasses. 
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398
 2011-06-01 15:32:10 +00:00
Stuart Hastings
6309f11cc6 Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695 
llvm-svn: 132396
 2011-06-01 14:04:17 +00:00
Joerg Sonnenberger
ffa79cb359 Add new -d option to tblgen. It writes a make(1)-style dependency file. 
llvm-svn: 132395
 2011-06-01 13:10:15 +00:00
Nadav Rotem
111ad2f6ce This patch is another step in the direction of adding vector select. In this 
patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization.  This flag will be removed when the transition is
complete.

llvm-svn: 132394
 2011-06-01 12:51:46 +00:00
Stuart Hastings
fdc9e4af68 FGETSIGN support for x86, using movmskps/pd. Will be enabled with a 
patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388
 2011-06-01 04:39:42 +00:00