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479 Commits

Author SHA1 Message Date
Chris Lattner
1d15bef6ac Remove the SparcV8 backend. It has been renamed to be the Sparc backend. 
llvm-svn: 25992
 2006-02-05 06:33:29 +00:00
Chris Lattner
0ddab3fc99 Custom lower VAARG for the case when we are doing vaarg(double). In this 
case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.

llvm-svn: 25967
 2006-02-04 08:31:30 +00:00
Chris Lattner
6466bb23bc Fix a nasty typo that broke functions with big stack frames. 
llvm-svn: 25966
 2006-02-04 08:04:21 +00:00
Chris Lattner
bb656b4730 fix a bug in my last checkin 
llvm-svn: 25965
 2006-02-04 07:48:46 +00:00
Chris Lattner
921ddbae1f add a note 
llvm-svn: 25962
 2006-02-04 07:07:31 +00:00
Chris Lattner
3b39e70a72 Two changes: 
1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
   ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
   up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.

llvm-svn: 25961
 2006-02-04 06:58:46 +00:00
Chris Lattner
255ef92e53 Teach sparc to fold loads/stores into copies. 
Remove the dead getRegClassForType method
minor formating changes.

llvm-svn: 25936
 2006-02-03 07:06:25 +00:00
Chris Lattner
590c0d8621 Implement isLoadFromStackSlot and isStoreToStackSlot 
llvm-svn: 25932
 2006-02-03 06:44:54 +00:00
Chris Lattner
95fe9f5df2 %fcc is not an alias for %fcc0 
llvm-svn: 25906
 2006-02-02 08:02:20 +00:00
Chris Lattner
f5c935f882 correct an opcode 
llvm-svn: 25905
 2006-02-02 07:56:15 +00:00
Evan Cheng
f115c17f23 Allow the specification of explicit alignments for constant pool entries. 
llvm-svn: 25855
 2006-01-31 22:23:14 +00:00
Chris Lattner
b54e4baa26 add a missing break that caused a lot of failures last night :( 
llvm-svn: 25851
 2006-01-31 17:20:06 +00:00
Chris Lattner
798747b798 okay, one more 
llvm-svn: 25847
 2006-01-31 07:45:45 +00:00
Chris Lattner
c831039792 another note 
llvm-svn: 25846
 2006-01-31 07:45:08 +00:00
Chris Lattner
5d718dbc1e More notes 
llvm-svn: 25845
 2006-01-31 07:43:33 +00:00
Chris Lattner
e0d5ccdecf another one 
llvm-svn: 25844
 2006-01-31 07:38:32 +00:00
Chris Lattner
66751830ed add a note 
llvm-svn: 25843
 2006-01-31 07:37:20 +00:00
Chris Lattner
1a0bf14366 add conditional moves of float and double values on int/fp condition codes. 
llvm-svn: 25842
 2006-01-31 07:26:55 +00:00
Chris Lattner
769e683663 treat conditional branches the same way as conditional moves (giving them 
an operand that contains the condcode), making things significantly simpler.

llvm-svn: 25840
 2006-01-31 06:56:30 +00:00
Chris Lattner
a999c688d5 compactify all of the integer conditional moves into one instruction that takes 
a CC as an operand.  Much smaller, much happier.

llvm-svn: 25839
 2006-01-31 06:49:09 +00:00
Chris Lattner
5aade7535c Add immediate forms of integer cmovs 
llvm-svn: 25838
 2006-01-31 06:24:29 +00:00
Chris Lattner
c1b80cb2fe Shrinkify 
llvm-svn: 25837
 2006-01-31 06:18:16 +00:00
Chris Lattner
fcd00875a9 Add the full complement of conditional moves of integer registers. 
llvm-svn: 25834
 2006-01-31 05:26:36 +00:00
Chris Lattner
9d29548015 Compile this: 
void %X(int %A) {
        %C = setlt int %A, 123          ; <bool> [#uses=1]
        br bool %C, label %T, label %F

T:              ; preds = %0
        call int %main( int 0 )         ; <int>:0 [#uses=0]
        ret void

F:              ; preds = %0
        ret void
}

to this:

X:
        save -96, %o6, %o6
        subcc %i0, 122, %l0
        bg .LBBX_2      ! F
        nop
...

not this:

X:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        subcc %i0, 122, %l2
        bg .LBBX_4      !
        nop
.LBBX_3:        !
        or %g0, %l0, %l1
.LBBX_4:        !
        subcc %l1, 0, %l0
        bne .LBBX_2     ! F
        nop

llvm-svn: 25833
 2006-01-31 05:05:52 +00:00
Chris Lattner
213a7b78fb I don't see why this optimization isn't safe, but it isn't, so disable it 
llvm-svn: 25829
 2006-01-31 02:45:52 +00:00
Chris Lattner
3ae06dac75 Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night 
llvm-svn: 25819
 2006-01-30 22:20:49 +00:00
Chris Lattner
baa47e9a6e Revamp the ICC/FCC reading instructions to be parameterized in terms of the 
SPARC condition codes, not in terms of the DAG condcodes.  This allows us to
write nice clean patterns for cmovs/branches.

llvm-svn: 25815
 2006-01-30 07:43:04 +00:00
Chris Lattner
7925da8b3b Compile: 
uint %test(uint %X) {
        %Y = call uint %llvm.ctpop.i32(uint %X)
        ret uint %Y
}

to:

test:
        save -96, %o6, %o6
        sll %i0, 0, %l0
        popc %l0, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of to 40 logical ops.  Note the shift-by-zero that clears the top
part of the 64-bit V9 register.

Testcase here: CodeGen/SparcV8/ctpop.ll

llvm-svn: 25814
 2006-01-30 06:14:02 +00:00
Chris Lattner
0c7df7e9d1 If the target has V9 instructions, this pass is a noop, don't bother 
running it.

llvm-svn: 25811
 2006-01-30 05:51:14 +00:00
Chris Lattner
69658ab9a8 When in v9 mode, emit fabsd/fnegd/fmovd 
llvm-svn: 25810
 2006-01-30 05:48:37 +00:00
Chris Lattner
98667e5f6a First step towards V9 instructions in the V8 backend, two conditional move 
patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}

llvm-svn: 25809
 2006-01-30 05:35:57 +00:00
Chris Lattner
8b5958a832 Two changes: 
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)

llvm-svn: 25807
 2006-01-30 04:57:43 +00:00
Chris Lattner
f0ea60bc01 When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold 
the two operations together.  This allows us to compile this:

void %two(int %a, int* %b) {
        %tmp.2 = seteq int %a, 0
        %tmp.0.0 = select bool %tmp.2, int 10, int 20
        store int %tmp.0.0, int* %b
        ret void
}

into:

two:
        save -96, %o6, %o6
        or %g0, 20, %l0
        or %g0, 10, %l1
        subcc %i0, 0, %l2
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        st %l1, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

instead of:

two:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        or %g0, 20, %l2
        or %g0, 10, %l3
        subcc %i0, 0, %l4
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        subcc %l1, 0, %l0
        bne .LBBtwo_4   ! entry
        nop
.LBBtwo_3:      ! entry
        or %g0, %l2, %l3
.LBBtwo_4:      ! entry
        st %l3, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 25806
 2006-01-30 04:34:44 +00:00
Chris Lattner
a44182300b Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
llvm-svn: 25803
 2006-01-30 04:09:27 +00:00
Chris Lattner
354340b1b1 Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes, 
allowing redundant and's to be eliminated by the dag combiner.

llvm-svn: 25800
 2006-01-30 03:51:45 +00:00
Chris Lattner
ab3ad7d4ef Use V8ISD::CALL instead of ISD::CALL 
llvm-svn: 25716
 2006-01-27 23:30:03 +00:00
Chris Lattner
c245c32022 initialize member vars 
llvm-svn: 25712
 2006-01-27 22:38:36 +00:00
Nate Begeman
d2c6fbef4a Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696
 2006-01-27 21:09:22 +00:00
Evan Cheng
77885c204d Subtarget feature can now set any variable to any value 
llvm-svn: 25678
 2006-01-27 08:09:42 +00:00
Chris Lattner
20d4194a0d PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Chris Lattner
0204d70798 Rest of subtarget support, remove references to ppc 
llvm-svn: 25642
 2006-01-26 07:22:22 +00:00
Chris Lattner
eb424bfbca Add trivial subtarget support 
llvm-svn: 25641
 2006-01-26 06:51:21 +00:00
Evan Cheng
7da6daadc7 Set SchedulingForLatency to be the default scheduling preference for all. 
llvm-svn: 25607
 2006-01-25 18:52:42 +00:00
Nate Begeman
c29fac7fce First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606
 2006-01-25 18:21:52 +00:00
Evan Cheng
c368fb710f Default scheduling preference is SchedulingForLatency. 
llvm-svn: 25603
 2006-01-25 09:15:54 +00:00
Chris Lattner
39bdbf2ad2 remove the V8 simple isel 
llvm-svn: 25534
 2006-01-23 07:20:15 +00:00
Chris Lattner
aafc339b4e Add explicit #includes of <iostream> 
llvm-svn: 25515
 2006-01-22 23:41:00 +00:00
Chris Lattner
adff158fbd Add explicit #includes of <iostream> 
llvm-svn: 25509
 2006-01-22 22:53:01 +00:00
Chris Lattner
b15de45374 implement support for f32 arguments past the first 6 words 
llvm-svn: 25450
 2006-01-19 07:22:29 +00:00
Chris Lattner
1a1c43d70c Silly Sparc is big endian. If we have to load args out of incoming stack slots 
that are smaller than an int, make sure to adjust the frame pointer to take
this into consideration.

llvm-svn: 25351
 2006-01-16 01:40:00 +00:00